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lucien-nxpcfriedt
lucien-nxp
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boards: nxp: rt1180: migrate mpu setting under board folder
- add NXP_BOARD_SPECIFIC_MPU_SETTINGS kconfig to provide a switch for developer if they want to use private mpu settings CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==1 | NXP default setting CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==0 | User specific - Use DT function to get memory base address and region size for cm7 - CM33 use dts to set mpu settings - Add REGION_CUSTOMED_MEMORY_SIZE macro provide a common mapping ways to map actual memory_size_kb to "region_size" - The settings of the unified memory on cm33/cm7 cores: ocram1/flexspi2 -> REGION_RAM_NOCACHE_ATTR ocram2/dtcm -> REGION_RAM_NOCACHE_ATTR flexspi/itcm -> REGION_FLASH_ATTR Signed-off-by: Lucien Zhao <[email protected]>
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‎arch/arm/core/mpu/arm_mpu.c‎

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Original file line numberDiff line numberDiff line change
@@ -147,6 +147,11 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index)
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region_conf = _BUILD_REGION_CONF(region[idx], REGION_IO_ATTR);
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break;
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#endif
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#ifdef REGION_DEVICE_ATTR
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case DT_MEM_ARM_MPU_DEVICE:
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region_conf = _BUILD_REGION_CONF(region[idx], REGION_DEVICE_ATTR);
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break;
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#endif
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#ifdef REGION_EXTMEM_ATTR
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case DT_MEM_ARM_MPU_EXTMEM:
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region_conf = _BUILD_REGION_CONF(region[idx], REGION_EXTMEM_ATTR);

‎boards/nxp/mimxrt1180_evk/CMakeLists.txt‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,23 @@
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#
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# Copyright 2024 NXP
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# Copyright 2024-2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_library()
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zephyr_library_sources(board.c)
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if(CONFIG_SOC_MIMXRT1189_CM33)
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zephyr_linker_sources(DTCM_SECTION cm33/dtcm.ld)
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endif()
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if(CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS)
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if(CONFIG_SOC_MIMXRT1189_CM7)
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zephyr_sources(cm7/mpu_regions.c)
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zephyr_linker_sources(DTCM_SECTION cm7/dtcm.ld)
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endif()
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endif()
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1021
if(CONFIG_NXP_IMXRT_BOOT_HEADER)
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if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33)
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OR (DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7)))

‎boards/nxp/mimxrt1180_evk/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -20,3 +20,11 @@ config CM7_FLEXSPI_OFFSET
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default 0x28000000
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help
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This is the FlexSPI offset for CM7.
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config NXP_BOARD_SPECIFIC_MPU_SETTINGS
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bool "Use default MPU settings for NXP boards"
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default y if CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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help
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Enable this option to use the default MPU settings for NXP boards.
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This will configure the MPU regions according to the board's memory
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map and peripherals.

‎soc/nxp/imxrt/imxrt118x/m33/dtcm.ld‎ renamed to ‎boards/nxp/mimxrt1180_evk/cm33/dtcm.ld‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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/*
2-
* Copyright 2024 NXP
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* Copyright 2024-2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/

‎boards/nxp/mimxrt1180_evk/cm7/dtcm.ld‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
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/*
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* Copyright 2024-2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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*(NonCacheable)

‎boards/nxp/mimxrt1180_evk/cm7/mpu_regions.c‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
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#define MEMORY_REGION_SIZE_KB(SIZE) (SIZE / 1024)
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#define ITCM_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(itcm), 0)
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#define DTCM_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(dtcm), 0)
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#define OCRAM1_SHM_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(ocram1), 0)
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#define OCRAM2_SHM_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(ocram2), 0)
16+
#define HYPER_RAM_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(flexspi2), 1)
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#define QSPI_FLASH_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(flexspi), 1)
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#define PERIPHERAL_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(peripheral), 0)
19+
20+
#define REGION_ITCM_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(itcm), 0)
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#define REGION_ITCM_SIZE \
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REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(ITCM_SIZE))
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#define REGION_DTCM_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(dtcm), 0)
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#define REGION_DTCM_SIZE \
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REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(DTCM_SIZE))
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#define REGION_OCRAM1_SHM_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(ocram1), 0)
27+
#define REGION_OCRAM1_SHM_SIZE \
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REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(OCRAM1_SHM_SIZE))
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#define REGION_OCRAM2_SHM_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(ocram2), 0)
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#define REGION_OCRAM2_SHM_SIZE \
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REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(OCRAM2_SHM_SIZE))
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#define REGION_HYPER_RAM_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi2), 1)
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#define REGION_HYPER_RAM_SIZE \
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REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(HYPER_RAM_SIZE))
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#define REGION_QSPI_FLASH_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi), 1)
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#define REGION_QSPI_FLASH_SIZE \
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REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(QSPI_FLASH_SIZE))
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#define REGION_PERIPHERAL_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(peripheral), 0)
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#define REGION_PERIPHERAL_SIZE \
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REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(PERIPHERAL_SIZE))
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static const struct arm_mpu_region mpu_regions[] = {
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/*
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* Add "UNMAPPED" region to deny access to whole address space to
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* workaround speculative prefetch.
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* Refer to Arm errata 1013783-B for more details.
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*/
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MPU_REGION_ENTRY("UNMAPPED", 0,
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{REGION_4G | MPU_RASR_XN_Msk | P_NA_U_NA_Msk}),
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(itcm), okay)
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MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_ITCM_SIZE)),
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(dtcm), okay)
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MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,
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REGION_RAM_NOCACHE_ATTR(REGION_DTCM_SIZE)),
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ocram1), okay)
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MPU_REGION_ENTRY("OCRAM1", REGION_OCRAM1_SHM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_OCRAM1_SHM_SIZE)),
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#endif
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66+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ocram2), okay)
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MPU_REGION_ENTRY("OCRAM2", REGION_OCRAM2_SHM_BASE_ADDRESS,
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REGION_RAM_NOCACHE_ATTR(REGION_OCRAM2_SHM_SIZE)),
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#endif
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71+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(hyperram0), okay)
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MPU_REGION_ENTRY("HYPER_RAM", REGION_HYPER_RAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_HYPER_RAM_SIZE)),
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(w25q128jw), okay)
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MPU_REGION_ENTRY("QSPI_FLASH", REGION_QSPI_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_QSPI_FLASH_SIZE)),
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#endif
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81+
MPU_REGION_ENTRY("PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
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REGION_PPB_ATTR(REGION_PERIPHERAL_SIZE)),
83+
};
84+
85+
const struct arm_mpu_config mpu_config = {
86+
.num_regions = ARRAY_SIZE(mpu_regions),
87+
.mpu_regions = mpu_regions,
88+
};

‎boards/nxp/mimxrt1180_evk/cm7_flash_boot.overlay‎

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Original file line numberDiff line numberDiff line change
@@ -10,3 +10,7 @@
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zephyr,code-partition = &slot1_partition;
1111
};
1212
};
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14+
&flexspi {
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status = "okay";
16+
};

‎boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,15 @@
181181
};
182182

183183
&flexspi {
184-
status = "okay";
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/*
185+
* If booting with XIP from FlexSPI flash, the flash memory will be initialized by the
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* bootloader in ROM.
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* If not configured by the ROM bootloader, the user must ensure the w25q128jw QSPI device
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* is enabled in the DTS, otherwise, the user must set 'status = "disabled";
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* Note: mpu_region.c uses the status property from the DTS to configure the
190+
* corresponding MPU settings.
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*/
192+
status = "disabled";
185193
ahb-prefetch;
186194
ahb-read-addr-opt;
187195
rx-clock-source = <1>;

‎boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts‎

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Original file line numberDiff line numberDiff line change
@@ -31,6 +31,35 @@
3131
/* Winbond W957A8MFYA5K */
3232
device_type = "memory";
3333
reg = <0x14000000 DT_SIZE_M(8)>;
34+
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
35+
/*
36+
* Currently, HyperRAM on this board must be accessed under XIP mode,
37+
* so that the ROM bootloader can initialize it by reading the XMCD configuration.
38+
* These XMCD configurations are stored in the default settings file
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* `xip/evkmimxrt1180_flexspi_nor_config.c`. (If modifications are needed,
40+
* please refer to the examples and the "System Boot" chapter in the
41+
* RT1180 Reference Manual.)
42+
* The CM33 core of the MIMXRT1180_EVK runs in XIP mode and uses the
43+
* HyperRAM space as the RAM region by default. Therefore, the status of the
44+
* full hyperram0 memory node is set to "okay" for cm33 core.
45+
* At this point, the CM7 core can also access the HyperRAM.
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* However, since the entire HyperRAM region is occupied in the CM33's DTS,
47+
* users can allocate the HyperRAM reasonably so that both cores (CM33 and CM7)
48+
* can use HyperRAM as their RAM region.
49+
*
50+
* If not configured by the ROM bootloader, the user must ensure the hyperram0
51+
* device is enabled in the DTS, otherwise, the user must set 'status = "disabled".
52+
* Note: mpu_region.c uses the status property from the DTS to configure the
53+
* corresponding MPU settings.
54+
*/
55+
status = "okay";
56+
};
57+
58+
qspi_flash: memory@38000000 {
59+
device_type = "memory";
60+
reg = <0x38000000 DT_SIZE_M(16)>;
61+
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_FLASH)>;
62+
status = "okay";
3463
};
3564
};
3665

@@ -114,3 +143,7 @@ temp_sensor: &tmpsns {
114143
&sai1 {
115144
status = "okay";
116145
};
146+
147+
&flexspi {
148+
status = "okay";
149+
};

‎boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,31 @@
2525
nxp,m7-partition = &slot1_partition;
2626
};
2727

28-
hyperram0: memory@04000000 {
28+
hyperram0: memory@4000000 {
2929
/* Winbond W957A8MFYA5K */
3030
device_type = "memory";
31-
reg = <0x04000000 DT_SIZE_M(8)>;
31+
reg = <0x4000000 DT_SIZE_M(8)>;
32+
/*
33+
* Currently, HyperRAM on this board must be accessed under XIP mode,
34+
* so that the ROM bootloader can initialize it by reading the XMCD configuration.
35+
* These XMCD configurations are stored in the default settings file
36+
* `xip/evkmimxrt1180_flexspi_nor_config.c`. (If modifications are needed,
37+
* please refer to the examples and the "System Boot" chapter in the
38+
* RT1180 Reference Manual.)
39+
* The CM33 core of the MIMXRT1180_EVK runs in XIP mode and uses the
40+
* HyperRAM space as the RAM region by default. Therefore, the status of the
41+
* full hyperram0 memory node is set to "okay" for cm33 core.
42+
* At this point, the CM7 core can also access the HyperRAM.
43+
* However, since the entire HyperRAM region is occupied in the CM33's DTS,
44+
* users can allocate the HyperRAM reasonably so that both cores (CM33 and CM7)
45+
* can use HyperRAM as their RAM region.
46+
*
47+
* If not configured by the ROM bootloader, the user must ensure the hyperram0
48+
* device is enabled in the DTS, otherwise, the user must set 'status = "disabled";
49+
* Note: mpu_region.c uses the status property from the DTS to configure the
50+
* corresponding MPU settings.
51+
*/
52+
status = "disabled";
3253
};
3354
};
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