drivers: clock_control: mcux_syscon: enable PDM clock control

Enable PDM clock control for NXP MCUX SoCs.

Signed-off-by: Zhaoxiang Jin <[email protected]>

Author: ZhaoxiangJin

drivers/clock_control/clock_control_mcux_syscon.c

@@ -136,6 +136,10 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 #endif /* CONFIG_SOC_FAMILY_MCXN */
 #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(rtc), okay) */
 
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pdm), okay)
+	CLOCK_EnableClock(kCLOCK_Micfil);
+#endif
+
 	return 0;
 }
 
@@ -571,6 +575,12 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		*rate = CLOCK_GetLpspiClkFreq(1);
 		break;
 #endif /* defined(CONFIG_SPI_NXP_LPSPI) */
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pdm), okay)
+	case MCUX_PDM_CLK:
+		*rate = CLOCK_GetMicfilClkFreq();
+		break;
+#endif
 	}
 
 	return 0;

include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2024 NXP
+ * Copyright 2020-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -129,4 +129,6 @@
 #define MCUX_LPSPI0_CLK MCUX_LPC_CLK_ID(0x17, 0x00)
 #define MCUX_LPSPI1_CLK MCUX_LPC_CLK_ID(0x17, 0x01)
 
+#define MCUX_PDM_CLK MCUX_LPC_CLK_ID(0x18, 0x00)
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */