Skip to content

Commit c7221cd

Browse files
le-quang168tiennguyenzg
le-quang168
authored and
tiennguyenzg
committed
dts: renesas: Add Clock Control support for RZ/A3UL, V2L
Add Clock Control nodes to Renesas RZ/A3UL, V2L devicetree Signed-off-by: Quang Le <[email protected]> Signed-off-by: Tien Nguyen <[email protected]>
1 parent 0ffad88 commit c7221cd

File tree

2 files changed

+342
-0
lines changed

2 files changed

+342
-0
lines changed

‎dts/arm/renesas/rz/rzv/r9a07g054.dtsi‎

Lines changed: 134 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <mem.h>
88
#include <freq.h>
99
#include <zephyr/dt-bindings/adc/adc.h>
10+
#include <zephyr/dt-bindings/clock/renesas_rzv_clock.h>
1011

1112
/ {
1213
compatible = "renesas,r9a07g054";
@@ -32,6 +33,12 @@
3233
};
3334
};
3435

36+
osc: osc {
37+
compatible = "fixed-clock";
38+
clock-frequency = <DT_FREQ_M(24)>;
39+
#clock-cells = <0>;
40+
};
41+
3542
soc {
3643
adc: adc@40059000 {
3744
compatible = "renesas,rz-adc-c";
@@ -44,6 +51,133 @@
4451
status = "disabled";
4552
};
4653

54+
cpg: clock-controller@41010000 {
55+
compatible = "renesas,rz-cpg";
56+
reg = <0x41010000 DT_SIZE_K(64)>;
57+
#clock-cells = <1>;
58+
status = "okay";
59+
60+
iclk: iclk {
61+
compatible = "fixed-clock";
62+
clock-frequency = <DT_FREQ_M(1200)>;
63+
#clock-cells = <0>;
64+
};
65+
66+
i2clk: i2clk {
67+
compatible = "fixed-clock";
68+
clock-frequency = <DT_FREQ_M(200)>;
69+
#clock-cells = <0>;
70+
};
71+
72+
gclk: gclk {
73+
compatible = "fixed-clock";
74+
clock-frequency = <DT_FREQ_M(500)>;
75+
#clock-cells = <0>;
76+
};
77+
78+
s0clk: s0clk {
79+
compatible = "fixed-clock";
80+
clock-frequency = <DT_FREQ_K(12)>;
81+
#clock-cells = <0>;
82+
};
83+
84+
spi0clk: spi0clk {
85+
compatible = "fixed-clock";
86+
clock-frequency = <DT_FREQ_M(200)>;
87+
#clock-cells = <0>;
88+
};
89+
90+
spi1clk: spi1clk {
91+
compatible = "fixed-clock";
92+
clock-frequency = <DT_FREQ_M(100)>;
93+
#clock-cells = <0>;
94+
};
95+
96+
sd0clk: sd0clk {
97+
compatible = "fixed-clock";
98+
clock-frequency = <DT_FREQ_M(533)>;
99+
#clock-cells = <0>;
100+
};
101+
102+
sd1clk: sd1clk {
103+
compatible = "fixed-clock";
104+
clock-frequency = <DT_FREQ_M(533)>;
105+
#clock-cells = <0>;
106+
};
107+
108+
m0clk: m0clk {
109+
compatible = "fixed-clock";
110+
clock-frequency = <DT_FREQ_M(200)>;
111+
#clock-cells = <0>;
112+
};
113+
114+
m1clk: m1clk {
115+
compatible = "fixed-clock";
116+
clock-frequency = <DT_FREQ_M(3000)>;
117+
#clock-cells = <0>;
118+
};
119+
120+
m2clk: m2clk {
121+
compatible = "fixed-clock";
122+
clock-frequency = <266500000>;
123+
#clock-cells = <0>;
124+
};
125+
126+
m3clk: m3clk {
127+
compatible = "fixed-clock";
128+
clock-frequency = <DT_FREQ_M(3000)>;
129+
#clock-cells = <0>;
130+
};
131+
132+
m4clk: m4clk {
133+
compatible = "fixed-clock";
134+
clock-frequency = <16656000>;
135+
#clock-cells = <0>;
136+
};
137+
138+
hpclk: hpclk {
139+
compatible = "fixed-clock";
140+
clock-frequency = <DT_FREQ_M(250)>;
141+
#clock-cells = <0>;
142+
};
143+
144+
tsuclk: tsuclk {
145+
compatible = "fixed-clock";
146+
clock-frequency = <DT_FREQ_M(80)>;
147+
#clock-cells = <0>;
148+
};
149+
150+
ztclk: ztclk {
151+
compatible = "fixed-clock";
152+
clock-frequency = <DT_FREQ_M(100)>;
153+
#clock-cells = <0>;
154+
};
155+
156+
p0clk: p0clk {
157+
compatible = "fixed-clock";
158+
clock-frequency = <DT_FREQ_M(100)>;
159+
#clock-cells = <0>;
160+
};
161+
162+
p1clk: p1clk {
163+
compatible = "fixed-clock";
164+
clock-frequency = <DT_FREQ_M(200)>;
165+
#clock-cells = <0>;
166+
};
167+
168+
p2clk: p2clk {
169+
compatible = "fixed-clock";
170+
clock-frequency = <DT_FREQ_M(100)>;
171+
#clock-cells = <0>;
172+
};
173+
174+
atclk: atclk {
175+
compatible = "fixed-clock";
176+
clock-frequency = <DT_FREQ_M(400)>;
177+
#clock-cells = <0>;
178+
};
179+
};
180+
47181
pinctrl: pin-controller@41030000 {
48182
compatible = "renesas,rzv-pinctrl";
49183
reg = <0x41030000 DT_SIZE_K(64)>;

‎dts/arm64/renesas/rz/rza/r9a07g063.dtsi‎

Lines changed: 208 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <zephyr/dt-bindings/gpio/gpio.h>
1212
#include <zephyr/dt-bindings/pwm/renesas_rz_pwm.h>
1313
#include <zephyr/dt-bindings/adc/adc.h>
14+
#include <zephyr/dt-bindings/clock/renesas_rza_clock.h>
1415

1516
/ {
1617
compatible = "renesas,r9a07g063";
@@ -38,9 +39,216 @@
3839
interrupt-parent = <&gic>;
3940
};
4041

42+
osc: osc {
43+
compatible = "fixed-clock";
44+
clock-frequency = <DT_FREQ_M(24)>;
45+
#clock-cells = <0>;
46+
};
47+
4148
soc {
4249
interrupt-parent = <&gic>;
4350

51+
cpg: clock-controller@11010000 {
52+
compatible = "renesas,rz-cpg";
53+
reg = <0x11010000 DT_SIZE_K(64)>;
54+
clocks = <&osc>;
55+
#clock-cells = <1>;
56+
status = "okay";
57+
58+
pll1: pll1 {
59+
compatible = "renesas,rz-cpg-pll";
60+
clock-frequency = <DT_FREQ_M(1000)>;
61+
#clock-cells = <1>;
62+
};
63+
64+
pll2_1600: pll2-1600 {
65+
compatible = "renesas,rz-cpg-pll";
66+
clock-frequency = <DT_FREQ_M(1600)>;
67+
#clock-cells = <1>;
68+
};
69+
70+
pll2_533: pll2-533 {
71+
compatible = "renesas,rz-cpg-pll";
72+
clock-frequency = <DT_FREQ_M(533)>;
73+
#clock-cells = <1>;
74+
};
75+
76+
pll3_1600: pll3-1600 {
77+
compatible = "renesas,rz-cpg-pll";
78+
clock-frequency = <DT_FREQ_M(1600)>;
79+
#clock-cells = <1>;
80+
};
81+
82+
pll3_533: pll3-533 {
83+
compatible = "renesas,rz-cpg-pll";
84+
clock-frequency = <DT_FREQ_M(533)>;
85+
#clock-cells = <1>;
86+
};
87+
88+
pll3_400: pll3-400 {
89+
compatible = "renesas,rz-cpg-pll";
90+
clock-frequency = <DT_FREQ_M(400)>;
91+
#clock-cells = <1>;
92+
};
93+
94+
pll4: pll4 {
95+
compatible = "renesas,rz-cpg-pll";
96+
clock-frequency = <DT_FREQ_M(1600)>;
97+
#clock-cells = <1>;
98+
};
99+
100+
pll5_1500: pll5-1500 {
101+
compatible = "renesas,rz-cpg-pll";
102+
clock-frequency = <DT_FREQ_M(1500)>;
103+
#clock-cells = <1>;
104+
};
105+
106+
pll5_500: pll5-500 {
107+
compatible = "renesas,rz-cpg-pll";
108+
clock-frequency = <DT_FREQ_M(500)>;
109+
#clock-cells = <1>;
110+
};
111+
112+
pll6: pll6 {
113+
compatible = "renesas,rz-cpg-pll";
114+
clock-frequency = <DT_FREQ_M(500)>;
115+
#clock-cells = <1>;
116+
};
117+
118+
iclk: iclk {
119+
compatible = "renesas,rz-cpg-clock";
120+
clocks = <&pll1 1>;
121+
div = <1>;
122+
#clock-cells = <0>;
123+
};
124+
125+
sd0clk: sd0clk {
126+
compatible = "renesas,rz-cpg-clock";
127+
clocks = <&pll2_533 2>;
128+
div = <1>;
129+
#clock-cells = <0>;
130+
};
131+
132+
sd1clk: sd1clk {
133+
compatible = "renesas,rz-cpg-clock";
134+
clocks = <&pll2_1600 4>;
135+
div = <1>;
136+
#clock-cells = <0>;
137+
};
138+
139+
p0clk: p0clk {
140+
compatible = "renesas,rz-cpg-clock";
141+
clocks = <&pll2_1600 16>;
142+
div = <1>;
143+
#clock-cells = <0>;
144+
};
145+
146+
tsuclk: tsuclk {
147+
compatible = "renesas,rz-cpg-clock";
148+
clocks = <&pll2_1600 20>;
149+
div = <1>;
150+
#clock-cells = <0>;
151+
};
152+
153+
atclk: atclk {
154+
compatible = "renesas,rz-cpg-clock";
155+
clocks = <&pll3_1600 4>;
156+
div = <1>;
157+
#clock-cells = <0>;
158+
};
159+
160+
i2clk: i2clk {
161+
compatible = "renesas,rz-cpg-clock";
162+
clocks = <&pll3_1600 8>;
163+
div = <1>;
164+
#clock-cells = <0>;
165+
};
166+
167+
p1clk: p1clk {
168+
compatible = "renesas,rz-cpg-clock";
169+
clocks = <&pll3_1600 8>;
170+
div = <1>;
171+
#clock-cells = <0>;
172+
};
173+
174+
m0clk: m0clk {
175+
compatible = "renesas,rz-cpg-clock";
176+
clocks = <&pll3_1600 8>;
177+
div = <1>;
178+
#clock-cells = <0>;
179+
};
180+
181+
ztclk: ztclk {
182+
compatible = "renesas,rz-cpg-clock";
183+
clocks = <&pll3_1600 16>;
184+
div = <1>;
185+
#clock-cells = <0>;
186+
};
187+
188+
p2clk: p2clk {
189+
compatible = "renesas,rz-cpg-clock";
190+
clocks = <&pll3_1600 16>;
191+
div = <1>;
192+
#clock-cells = <0>;
193+
};
194+
195+
spi0clk: spi0clk {
196+
compatible = "renesas,rz-cpg-clock";
197+
clocks = <&pll3_533 2>;
198+
div = <2>;
199+
#clock-cells = <0>;
200+
};
201+
202+
spi1clk: spi1clk {
203+
compatible = "renesas,rz-cpg-clock";
204+
clocks = <&pll3_533 4>;
205+
div = <2>;
206+
#clock-cells = <0>;
207+
};
208+
209+
m2clk: m2clk {
210+
compatible = "renesas,rz-cpg-clock";
211+
clocks = <&pll3_533 2>;
212+
div = <1>;
213+
#clock-cells = <0>;
214+
};
215+
216+
oc0clk: oc0clk {
217+
compatible = "renesas,rz-cpg-clock";
218+
clocks = <&pll3_400 2>;
219+
div = <1>;
220+
#clock-cells = <0>;
221+
};
222+
223+
oc1clk: oc1clk {
224+
compatible = "renesas,rz-cpg-clock";
225+
clocks = <&pll3_400 4>;
226+
div = <1>;
227+
#clock-cells = <0>;
228+
};
229+
230+
s0clk: s0clk {
231+
compatible = "renesas,rz-cpg-clock";
232+
clocks = <&pll4 2>;
233+
div = <1>;
234+
#clock-cells = <0>;
235+
};
236+
237+
m3clk: m3clk {
238+
compatible = "renesas,rz-cpg-clock";
239+
clocks = <&pll5_1500 1>;
240+
div = <2>;
241+
#clock-cells = <0>;
242+
};
243+
244+
hpclk: hpclk {
245+
compatible = "renesas,rz-cpg-clock";
246+
clocks = <&pll6 2>;
247+
div = <1>;
248+
#clock-cells = <0>;
249+
};
250+
};
251+
44252
gic: interrupt-controller@11900000 {
45253
compatible = "arm,gic-v3", "arm,gic";
46254
reg = <0x11900000 0x10000>, /* GICD */

0 commit comments

Comments
 (0)