drivers: dma stm32U5 GPDMA keeps the channel busy if overriden

For the stm32U5 serie, the busy flag is handled as other serie.
When the DMA is overriden by other HAL drivers, the busy flag
is not considered.
Refer to #47645
There is no Mux for this GPDMA and fixed 16 channels.

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

drivers/dma/dma_stm32u5.c

@@ -230,8 +230,12 @@ static void dma_stm32_irq_handler(const struct device *dev, uint32_t id)
 	__ASSERT_NO_MSG(id < config->max_streams);
 
 	stream = &config->streams[id];
-	/* Exit if stream is no more busy */
-	if (stream->busy == false) {
+	/* The busy channel is pertinent if not overridden by the HAL */
+	if ((stream->hal_override != true) && (stream->busy == false)) {
+		/*
+		 * When DMA channel is not overridden by HAL,
+		 * ignore irq if the channel is not busy anymore
+		 */
 		dma_stm32_clear_stream_irq(dev, id);
 		return;
 	}
@@ -246,9 +250,6 @@ static void dma_stm32_irq_handler(const struct device *dev, uint32_t id)
 		}
 		stream->dma_callback(dev, stream->user_data, callback_arg, 0);
 	} else if (stm32_dma_is_tc_irq_active(dma, id)) {
-#ifdef CONFIG_DMAMUX_STM32
-		stream->busy = false;
-#endif
 		/* Let HAL DMA handle flags on its own */
 		if (!stream->hal_override) {
 			dma_stm32_clear_tc(dma, id);
@@ -540,6 +541,9 @@ static int dma_stm32_reload(const struct device *dev, uint32_t id,
 				     size / stream->dst_size);
 	}
 
+	/* When reloading the dma, the stream is busy again before enabling */
+	stream->busy = true;
+
 	stm32_dma_enable_stream(dma, id);
 
 	return 0;
@@ -549,6 +553,7 @@ static int dma_stm32_start(const struct device *dev, uint32_t id)
 {
 	const struct dma_stm32_config *config = dev->config;
 	DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
+	struct dma_stm32_stream *stream;
 
 	/* Give channel from index 0 */
 	id = id - STM32_DMA_STREAM_OFFSET;
@@ -558,6 +563,10 @@ static int dma_stm32_start(const struct device *dev, uint32_t id)
 		return -EINVAL;
 	}
 
+	/* When starting the dma, the stream is busy before enabling */
+	stream = &config->streams[id];
+	stream->busy = true;
+
 	dma_stm32_clear_stream_irq(dev, id);
 
 	stm32_dma_enable_stream(dma, id);
@@ -578,11 +587,11 @@ static int dma_stm32_stop(const struct device *dev, uint32_t id)
 		return -EINVAL;
 	}
 
+	LL_DMA_DisableIT_TC(dma, dma_stm32_id_to_stream(id));
+
 	dma_stm32_clear_stream_irq(dev, id);
 	dma_stm32_disable_stream(dma, id);
 
-	LL_DMA_DisableIT_TC(dma, dma_stm32_id_to_stream(id));
-
 	/* Finally, flag stream as free */
 	stream->busy = false;
 
@@ -715,16 +724,9 @@ static void dma_stm32_config_irq_0(const struct device *dev)
 	DMA_STM32_IRQ_CONNECT(0, 2);
 	DMA_STM32_IRQ_CONNECT(0, 3);
 	DMA_STM32_IRQ_CONNECT(0, 4);
-#if DT_INST_IRQ_HAS_IDX(0, 5)
 	DMA_STM32_IRQ_CONNECT(0, 5);
-#if DT_INST_IRQ_HAS_IDX(0, 6)
 	DMA_STM32_IRQ_CONNECT(0, 6);
-#if DT_INST_IRQ_HAS_IDX(0, 7)
 	DMA_STM32_IRQ_CONNECT(0, 7);
-#endif /* DT_INST_IRQ_HAS_IDX(0, 5) */
-#endif /* DT_INST_IRQ_HAS_IDX(0, 6) */
-#endif /* DT_INST_IRQ_HAS_IDX(0, 7) */
-/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
 	DMA_STM32_IRQ_CONNECT(0, 8);
 	DMA_STM32_IRQ_CONNECT(0, 9);
 	DMA_STM32_IRQ_CONNECT(0, 10);