dts: arm: sifli: sf32lb52x: define gpioa nodes

Add nodes for the GPIO controller (controlling pins PA00-44). Naming is
a bit confusing. In some places you'll find HPSYS_GPIO, other GPIO1,
pins are named PA00-PA44... I've chosen "GPIOA". Because the Zephyr GPIO
API assumes a maximum of 32 pins per controller, we have to split the
controller into 32-bit wide blocks. In reality, the controller
internally works like that (see the `reg` addresses), however, the whole
block is clocked by a single RCC _switch_.

Signed-off-by: Gerard Marull-Paretas <[email protected]>

Author: gmarull

dts/arm/sifli/sf32lb52x.dtsi

@@ -7,6 +7,7 @@
 #include <freq.h>
 
 #include <zephyr/dt-bindings/clock/sf32lb52x-clocks.h>
+#include <zephyr/dt-bindings/pinctrl/sf32lb52x-pinctrl.h>
 
 / {
 	cpus {
@@ -118,6 +119,41 @@
 			status = "disabled";
 		};
 
+		gpioa: gpio@500a0000 {
+			compatible = "sifli,sf32lb-gpio-parent";
+			reg = <0x500a0000 0x1000>;
+			ranges = <0x0 0x500a0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&rcc_clk SF32LB52X_CLOCK_GPIO1>;
+			interrupts = <84 0>;
+
+			/*
+			 * Split into 32 pin blocks due to Zephyr requiring GPIO
+			 * ports to have a maximum of 32 pins. This is a
+			 * Zephyrism, but it is what it is!
+			 */
+			gpioa_00_31: gpio@0 {
+				compatible = "sifli,sf32lb-gpio";
+				reg = <0x0 0x6c>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				ngpios = <32>;
+				sifli,pinmuxs = <&pinctrl SF32LB_PORT_PA 0x0>;
+				status = "disabled";
+			};
+
+			gpioa_32_44: gpio@80 {
+				compatible = "sifli,sf32lb-gpio";
+				reg = <0x80 0x6c>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				ngpios = <13>;
+				sifli,pinmuxs = <&pinctrl SF32LB_PORT_PA 0x80>;
+				status = "disabled";
+			};
+		};
+
 		cfg: syscon@5000b000 {
 			compatible = "sifli,sf32lb-cfg", "syscon";
 			reg = <0x5000b000 0x1000>;