dts: xtensa: add imx8qm and imx8qxp DTSI variants

imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.

One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:

"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"

To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).

Signed-off-by: Laurentiu Mihalcea <[email protected]>

Author: LaurentiuM1234

boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_imx8.dtsi>
+#include <nxp/nxp_imx8qm.dtsi>
 #include "imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi"
 
 / {

boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_imx8.dtsi>
+#include <nxp/nxp_imx8qxp.dtsi>
 #include "imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi"
 
 / {
@@ -31,7 +31,3 @@
 	pinctrl-0 = <&sai1_default>;
 	pinctrl-names = "default";
 };
-
-&irqsteer {
-	reg = <0x51080000 DT_SIZE_K(64)>;
-};

dts/xtensa/nxp/nxp_imx8.dtsi

@@ -32,79 +32,6 @@
 		};
 	};
 
-	irqsteer: interrupt-controller@510a0000 {
-		compatible = "nxp,irqsteer-intc";
-		reg = <0x510a0000 DT_SIZE_K(64)>;
-		power-domains = <&irqstr_pd>;
-
-		#size-cells = <0>;
-		#address-cells = <1>;
-
-		master0: interrupt-controller@0 {
-			compatible = "nxp,irqsteer-master";
-			reg = <0>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 19 0 0>;
-		};
-
-		master1: interrupt-controller@1 {
-			compatible = "nxp,irqsteer-master";
-			reg = <1>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 20 0 0>;
-		};
-
-		master2: interrupt-controller@2 {
-			compatible = "nxp,irqsteer-master";
-			reg = <2>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 21 0 0>;
-		};
-
-		master3: interrupt-controller@3 {
-			compatible = "nxp,irqsteer-master";
-			reg = <3>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 22 0 0>;
-		};
-
-		master4: interrupt-controller@4 {
-			compatible = "nxp,irqsteer-master";
-			reg = <4>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 23 0 0>;
-		};
-
-		master5: interrupt-controller@5 {
-			compatible = "nxp,irqsteer-master";
-			reg = <5>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 24 0 0>;
-		};
-
-		master6: interrupt-controller@6 {
-			compatible = "nxp,irqsteer-master";
-			reg = <6>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 25 0 0>;
-		};
-
-		master7: interrupt-controller@7 {
-			compatible = "nxp,irqsteer-master";
-			reg = <7>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupts-extended = <&clic 26 0 0>;
-		};
-	};
-
 	sram0: memory@92400000 {
 		device_type = "memory";
 		compatible = "mmio-sram";

dts/xtensa/nxp/nxp_imx8qm.dtsi

@@ -0,0 +1,83 @@
+/*
+ * Copyright 2021, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/nxp_imx8.dtsi>
+
+/ {
+	irqsteer: interrupt-controller@510a0000 {
+		compatible = "nxp,irqsteer-intc";
+		reg = <0x510a0000 DT_SIZE_K(64)>;
+		power-domains = <&irqstr_pd>;
+
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		master0: interrupt-controller@0 {
+			compatible = "nxp,irqsteer-master";
+			reg = <0>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 19 0 0>;
+		};
+
+		master1: interrupt-controller@1 {
+			compatible = "nxp,irqsteer-master";
+			reg = <1>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 20 0 0>;
+		};
+
+		master2: interrupt-controller@2 {
+			compatible = "nxp,irqsteer-master";
+			reg = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 21 0 0>;
+		};
+
+		master3: interrupt-controller@3 {
+			compatible = "nxp,irqsteer-master";
+			reg = <3>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 22 0 0>;
+		};
+
+		master4: interrupt-controller@4 {
+			compatible = "nxp,irqsteer-master";
+			reg = <4>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 23 0 0>;
+		};
+
+		master5: interrupt-controller@5 {
+			compatible = "nxp,irqsteer-master";
+			reg = <5>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 24 0 0>;
+		};
+
+		master6: interrupt-controller@6 {
+			compatible = "nxp,irqsteer-master";
+			reg = <6>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 25 0 0>;
+		};
+
+		master7: interrupt-controller@7 {
+			compatible = "nxp,irqsteer-master";
+			reg = <7>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 26 0 0>;
+		};
+	};
+};

dts/xtensa/nxp/nxp_imx8qxp.dtsi

@@ -0,0 +1,82 @@
+/*
+ * Copyright 2021, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_imx8.dtsi>
+
+/ {
+	irqsteer: interrupt-controller@51080000 {
+		compatible = "nxp,irqsteer-intc";
+		reg = <0x51080000 DT_SIZE_K(64)>;
+		power-domains = <&irqstr_pd>;
+
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		master0: interrupt-controller@0 {
+			compatible = "nxp,irqsteer-master";
+			reg = <0>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 19 0 0>;
+		};
+
+		master1: interrupt-controller@1 {
+			compatible = "nxp,irqsteer-master";
+			reg = <1>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 20 0 0>;
+		};
+
+		master2: interrupt-controller@2 {
+			compatible = "nxp,irqsteer-master";
+			reg = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 21 0 0>;
+		};
+
+		master3: interrupt-controller@3 {
+			compatible = "nxp,irqsteer-master";
+			reg = <3>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 22 0 0>;
+		};
+
+		master4: interrupt-controller@4 {
+			compatible = "nxp,irqsteer-master";
+			reg = <4>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 23 0 0>;
+		};
+
+		master5: interrupt-controller@5 {
+			compatible = "nxp,irqsteer-master";
+			reg = <5>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 24 0 0>;
+		};
+
+		master6: interrupt-controller@6 {
+			compatible = "nxp,irqsteer-master";
+			reg = <6>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 25 0 0>;
+		};
+
+		master7: interrupt-controller@7 {
+			compatible = "nxp,irqsteer-master";
+			reg = <7>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts-extended = <&clic 26 0 0>;
+		};
+	};
+};