dts: xtensa: intel: add dmic dts definitions

Add Intel dmic dai dts definitions for ace15, cavs15 and cavs25
platforms.

Add also pre dts cmake files as the dmic nodes use same address and emit
warnings otherwise.

Signed-off-by: Jaska Uimonen <[email protected]>

Author: Jaska Uimonen

boards/xtensa/intel_adsp_ace15_mtpm/pre_dt_board.cmake

@@ -0,0 +1,6 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
+# - dmic0: dmic0@10000 & dmic1: dmic1@10000
+list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")

boards/xtensa/intel_adsp_cavs15/pre_dt_board.cmake

@@ -0,0 +1,6 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
+# - dmic0: dmic0@10000 & dmic1: dmic1@10000
+list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")

boards/xtensa/intel_adsp_cavs25/pre_dt_board.cmake

@@ -0,0 +1,6 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
+# - dmic0: dmic0@10000 & dmic1: dmic1@10000
+list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")

dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi

@@ -316,6 +316,24 @@
 			status = "okay";
 		};
 
+		dmic0: dmic0@10000 {
+			compatible = "intel,dai-dmic";
+			reg = <0x10000 0x8000>;
+			shim = <0xC000>;
+			fifo = <0x0008>;
+			interrupts = <0x08 0 0>;
+			interrupt-parent = <&ace_intc>;
+		};
+
+		dmic1: dmic1@10000 {
+			compatible = "intel,dai-dmic";
+			reg = <0x10000 0x8000>;
+			shim = <0xC000>;
+			fifo = <0x0108>;
+			interrupts = <0x09 0 0>;
+			interrupt-parent = <&ace_intc>;
+		};
+
 		hub_ulp_domain: hub_ulp_domain {
 			compatible = "intel,adsp-power-domain";
 			lps = <&lps>;

dts/xtensa/intel/intel_adsp_cavs15.dtsi

@@ -286,5 +286,24 @@
 
 			status = "okay";
 		};
+
+		dmic0: dmic0@4000 {
+			compatible = "intel,dai-dmic";
+			reg = <0x4000 0x8000>;
+			shim = <0x1000>;
+			fifo = <0x0008>;
+			interrupts = <0x08 0 0>;
+			interrupt-parent = <&cavs_intc3>;
+		};
+
+		dmic1: dmic1@4000 {
+			compatible = "intel,dai-dmic";
+			reg = <0x4000 0x8000>;
+			shim = <0x1000>;
+			fifo = <0x0108>;
+			interrupts = <0x09 0 0>;
+			interrupt-parent = <&cavs_intc3>;
+		};
+
 	};
 };

dts/xtensa/intel/intel_adsp_cavs25.dtsi

@@ -266,5 +266,23 @@
 
 			status = "okay";
 		};
+
+		dmic0: dmic0@10000 {
+			compatible = "intel,dai-dmic";
+			reg = <0x10000 0x8000>;
+			shim = <0x71E80>;
+			fifo = <0x0008>;
+			interrupts = <0x08 0 0>;
+			interrupt-parent = <&cavs_intc3>;
+		};
+
+		dmic1: dmic1@10000 {
+			compatible = "intel,dai-dmic";
+			reg = <0x10000 0x8000>;
+			shim = <0x71E80>;
+			fifo = <0x0108>;
+			interrupts = <0x09 0 0>;
+			interrupt-parent = <&cavs_intc3>;
+		};
 	};
 };