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ithinuelkartben
ithinuel
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kartben
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arch: arm: cortex_m: Apply clang-format on cortex_m related code
This commit updates cortex_m related code to align it with the rules from .clang-format. This is done to simplify future changes in these files as we are about to implement use_switch support. Some rules conflict with checkpatch and therefore some small part of the code locally disable clang-format. Signed-off-by: Wilfried Chauveau <[email protected]>
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‎arch/arm/core/cortex_m/cmse/arm_core_cmse.c‎

Lines changed: 14 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99

1010
int arm_cmse_mpu_region_get(uint32_t addr)
1111
{
12-
cmse_address_info_t addr_info = cmse_TT((void *)addr);
12+
cmse_address_info_t addr_info = cmse_TT((void *)addr);
1313

1414
if (addr_info.flags.mpu_region_valid) {
1515
return addr_info.flags.mpu_region;
@@ -40,8 +40,7 @@ int arm_cmse_addr_readwrite_ok(uint32_t addr, int force_npriv)
4040
return arm_cmse_addr_read_write_ok(addr, force_npriv, 1);
4141
}
4242

43-
static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size,
44-
int force_npriv, int rw)
43+
static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size, int force_npriv, int rw)
4544
{
4645
int flags = 0;
4746

@@ -74,18 +73,18 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
7473

7574
int arm_cmse_mpu_nonsecure_region_get(uint32_t addr)
7675
{
77-
cmse_address_info_t addr_info = cmse_TTA((void *)addr);
76+
cmse_address_info_t addr_info = cmse_TTA((void *)addr);
7877

7978
if (addr_info.flags.mpu_region_valid) {
80-
return addr_info.flags.mpu_region;
79+
return addr_info.flags.mpu_region;
8180
}
8281

8382
return -EINVAL;
8483
}
8584

8685
int arm_cmse_sau_region_get(uint32_t addr)
8786
{
88-
cmse_address_info_t addr_info = cmse_TT((void *)addr);
87+
cmse_address_info_t addr_info = cmse_TT((void *)addr);
8988

9089
if (addr_info.flags.sau_region_valid) {
9190
return addr_info.flags.sau_region;
@@ -96,7 +95,7 @@ int arm_cmse_sau_region_get(uint32_t addr)
9695

9796
int arm_cmse_idau_region_get(uint32_t addr)
9897
{
99-
cmse_address_info_t addr_info = cmse_TT((void *)addr);
98+
cmse_address_info_t addr_info = cmse_TT((void *)addr);
10099

101100
if (addr_info.flags.idau_region_valid) {
102101
return addr_info.flags.idau_region;
@@ -107,13 +106,12 @@ int arm_cmse_idau_region_get(uint32_t addr)
107106

108107
int arm_cmse_addr_is_secure(uint32_t addr)
109108
{
110-
cmse_address_info_t addr_info = cmse_TT((void *)addr);
109+
cmse_address_info_t addr_info = cmse_TT((void *)addr);
111110

112111
return addr_info.flags.secure;
113112
}
114113

115-
static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
116-
int force_npriv, int rw)
114+
static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, int force_npriv, int rw)
117115
{
118116
cmse_address_info_t addr_info;
119117
if (force_npriv) {
@@ -122,8 +120,7 @@ static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
122120
addr_info = cmse_TTA((void *)addr);
123121
}
124122

125-
return rw ? addr_info.flags.nonsecure_readwrite_ok :
126-
addr_info.flags.nonsecure_read_ok;
123+
return rw ? addr_info.flags.nonsecure_readwrite_ok : addr_info.flags.nonsecure_read_ok;
127124
}
128125

129126
int arm_cmse_addr_nonsecure_read_ok(uint32_t addr, int force_npriv)
@@ -137,7 +134,7 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv)
137134
}
138135

139136
static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t size,
140-
int force_npriv, int rw)
137+
int force_npriv, int rw)
141138
{
142139
int flags = CMSE_NONSECURE;
143140

@@ -156,18 +153,14 @@ static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t s
156153
}
157154
}
158155

159-
int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
160-
int force_npriv)
156+
int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv)
161157
{
162-
return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
163-
force_npriv, 0);
158+
return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 0);
164159
}
165160

166-
int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
167-
int force_npriv)
161+
int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv)
168162
{
169-
return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
170-
force_npriv, 1);
163+
return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 1);
171164
}
172165

173166
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

‎arch/arm/core/cortex_m/coredump.c‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -7,31 +7,31 @@
77
#include <string.h>
88
#include <zephyr/debug/coredump.h>
99

10-
#define ARCH_HDR_VER 2
10+
#define ARCH_HDR_VER 2
1111

1212
uint32_t z_arm_coredump_fault_sp;
1313

1414
struct arm_arch_block {
1515
struct {
16-
uint32_t r0;
17-
uint32_t r1;
18-
uint32_t r2;
19-
uint32_t r3;
20-
uint32_t r12;
21-
uint32_t lr;
22-
uint32_t pc;
23-
uint32_t xpsr;
24-
uint32_t sp;
16+
uint32_t r0;
17+
uint32_t r1;
18+
uint32_t r2;
19+
uint32_t r3;
20+
uint32_t r12;
21+
uint32_t lr;
22+
uint32_t pc;
23+
uint32_t xpsr;
24+
uint32_t sp;
2525

2626
/* callee registers - optionally collected in V2 */
27-
uint32_t r4;
28-
uint32_t r5;
29-
uint32_t r6;
30-
uint32_t r7;
31-
uint32_t r8;
32-
uint32_t r9;
33-
uint32_t r10;
34-
uint32_t r11;
27+
uint32_t r4;
28+
uint32_t r5;
29+
uint32_t r6;
30+
uint32_t r7;
31+
uint32_t r8;
32+
uint32_t r9;
33+
uint32_t r10;
34+
uint32_t r11;
3535
} r;
3636
} __packed;
3737

@@ -76,12 +76,12 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
7676

7777
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
7878
if (esf->extra_info.callee) {
79-
arch_blk.r.r4 = esf->extra_info.callee->v1;
80-
arch_blk.r.r5 = esf->extra_info.callee->v2;
81-
arch_blk.r.r6 = esf->extra_info.callee->v3;
82-
arch_blk.r.r7 = esf->extra_info.callee->v4;
83-
arch_blk.r.r8 = esf->extra_info.callee->v5;
84-
arch_blk.r.r9 = esf->extra_info.callee->v6;
79+
arch_blk.r.r4 = esf->extra_info.callee->v1;
80+
arch_blk.r.r5 = esf->extra_info.callee->v2;
81+
arch_blk.r.r6 = esf->extra_info.callee->v3;
82+
arch_blk.r.r7 = esf->extra_info.callee->v4;
83+
arch_blk.r.r8 = esf->extra_info.callee->v5;
84+
arch_blk.r.r9 = esf->extra_info.callee->v6;
8585
arch_blk.r.r10 = esf->extra_info.callee->v7;
8686
arch_blk.r.r11 = esf->extra_info.callee->v8;
8787
}

‎arch/arm/core/cortex_m/cpu_idle.c‎

Lines changed: 21 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -30,27 +30,31 @@ void z_arm_cpu_idle_init(void)
3030
#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
3131
#define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
3232
#else
33-
#define ON_EXIT_IDLE_HOOK do {} while (false)
33+
#define ON_EXIT_IDLE_HOOK \
34+
do { \
35+
} while (false)
3436
#endif
3537

3638
#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
37-
#define SLEEP_IF_ALLOWED(wait_instr) do { \
38-
/* Skip the wait instr if on_enter_cpu_idle returns false */ \
39-
if (z_arm_on_enter_cpu_idle()) { \
40-
/* Wait for all memory transaction to complete */ \
41-
/* before entering low power state. */ \
42-
__DSB(); \
43-
wait_instr(); \
44-
/* Inline the macro provided by SoC-specific code */ \
45-
ON_EXIT_IDLE_HOOK; \
46-
} \
47-
} while (false)
39+
#define SLEEP_IF_ALLOWED(wait_instr) \
40+
do { \
41+
/* Skip the wait instr if on_enter_cpu_idle returns false */ \
42+
if (z_arm_on_enter_cpu_idle()) { \
43+
/* Wait for all memory transaction to complete */ \
44+
/* before entering low power state. */ \
45+
__DSB(); \
46+
wait_instr(); \
47+
/* Inline the macro provided by SoC-specific code */ \
48+
ON_EXIT_IDLE_HOOK; \
49+
} \
50+
} while (false)
4851
#else
49-
#define SLEEP_IF_ALLOWED(wait_instr) do { \
50-
__DSB(); \
51-
wait_instr(); \
52-
ON_EXIT_IDLE_HOOK; \
53-
} while (false)
52+
#define SLEEP_IF_ALLOWED(wait_instr) \
53+
do { \
54+
__DSB(); \
55+
wait_instr(); \
56+
ON_EXIT_IDLE_HOOK; \
57+
} while (false)
5458
#endif
5559

5660
#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE

‎arch/arm/core/cortex_m/debug.c‎

Lines changed: 11 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ bool z_arm_debug_monitor_event_error_check(void)
3535
printk("Null-pointer exception?\n");
3636
}
3737
__ASSERT((DWT->FUNCTION0 & DWT_FUNCTION_MATCHED_Msk) == 0,
38-
"MATCHED flag should have been cleared on read.");
38+
"MATCHED flag should have been cleared on read.");
3939

4040
return true;
4141
}
@@ -55,8 +55,8 @@ bool z_arm_debug_monitor_event_error_check(void)
5555
* so we add a build assert that catches it.
5656
*/
5757
BUILD_ASSERT(!(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE &
58-
(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
59-
"the size of the partition must be power of 2");
58+
(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
59+
"the size of the partition must be power of 2");
6060

6161
int z_arm_debug_enable_null_pointer_detection(void)
6262
{
@@ -81,20 +81,12 @@ int z_arm_debug_enable_null_pointer_detection(void)
8181
DWT->COMP0 = 0;
8282
DWT->COMP1 = CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1;
8383

84-
DWT->FUNCTION0 =
85-
((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
86-
|
87-
((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
88-
|
89-
((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
90-
;
91-
DWT->FUNCTION1 =
92-
((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
93-
|
94-
((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
95-
|
96-
((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
97-
;
84+
DWT->FUNCTION0 = ((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
85+
((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
86+
((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
87+
DWT->FUNCTION1 = ((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
88+
((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
89+
((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
9890
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
9991

10092
/* ASSERT that we have the comparator needed for the implementation */
@@ -106,13 +98,10 @@ int z_arm_debug_enable_null_pointer_detection(void)
10698
/* Use comparator 0, R/W access check */
10799
DWT->COMP0 = 0;
108100

109-
DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) &
110-
DWT_FUNCTION_FUNCTION_Msk;
111-
101+
DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) & DWT_FUNCTION_FUNCTION_Msk;
112102

113103
/* Set mask according to the desired size */
114-
DWT->MASK0 = 32 - __builtin_clzl(
115-
CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
104+
DWT->MASK0 = 32 - __builtin_clzl(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
116105
#endif
117106

118107
return 0;

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