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dts: arm: renesas: ra: Reorganize RA4M1 files
Extract common parts from `dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi` to support R7FA4M1AB3CFM. Signed-off-by: TOKITA Hiroshi <[email protected]>
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-338
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3 files changed

+370
-338
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‎dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi‎

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/*
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* Copyright (c) 2025 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <arm/renesas/ra/ra4/r7fa4m1ax.dtsi>
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/delete-node/ &ioport5;
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/delete-node/ &ioport6;
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/delete-node/ &ioport7;
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/delete-node/ &ioport8;
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/ {
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soc {
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flash-controller@407e0000 {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_K(256)>;
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi‎

Lines changed: 10 additions & 338 deletions
Original file line numberDiff line numberDiff line change
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/*
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* Copyright (c) 2024-2025 Renesas Electronics Corporation
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* Copyright (c) 2025 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/ra_clock.h>
8-
#include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
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#include <arm/renesas/ra/ra4/r7fa4m1ax.dtsi>
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1010
/ {
11-
soc {
12-
sram0: memory@20000000 {
13-
compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
16-
17-
flash-controller@407e0000 {
18-
reg = <0x407e0000 0x10000>;
19-
#address-cells = <1>;
20-
#size-cells = <1>;
21-
22-
flash0: flash@0 {
23-
compatible = "soc-nv-flash";
24-
reg = <0x0 DT_SIZE_K(256)>;
25-
};
26-
};
27-
28-
ioport6: gpio@400400c0 {
29-
compatible = "renesas,ra-gpio-ioport";
30-
reg = <0x400400c0 0x20>;
31-
port = <6>;
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gpio-controller;
33-
#gpio-cells = <2>;
34-
ngpios = <16>;
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status = "disabled";
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};
37-
38-
ioport7: gpio@400400e0 {
39-
compatible = "renesas,ra-gpio-ioport";
40-
reg = <0x400400e0 0x20>;
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port = <7>;
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gpio-controller;
43-
#gpio-cells = <2>;
44-
ngpios = <16>;
45-
status = "disabled";
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};
47-
48-
ioport8: gpio@40040100 {
49-
compatible = "renesas,ra-gpio-ioport";
50-
reg = <0x40040100 0x20>;
51-
port = <8>;
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gpio-controller;
53-
#gpio-cells = <2>;
54-
ngpios = <16>;
55-
status = "disabled";
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};
57-
58-
sci2: sci2@40070040 {
59-
compatible = "renesas,ra-sci";
60-
reg = <0x40070040 0x20>;
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clocks = <&pclka MSTPB 29>;
62-
status = "disabled";
63-
64-
uart {
65-
compatible = "renesas,ra-sci-uart";
66-
channel = <2>;
67-
status = "disabled";
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};
69-
};
70-
71-
adc@4005c000 {
72-
interrupts = <20 1>;
73-
channel-count = <25>;
74-
channel-available-mask = <0x3ff7fff>;
75-
};
76-
77-
port_irq5: external-interrupt@40006005 {
78-
compatible = "renesas,ra-external-interrupt";
79-
reg = <0x40006005 0x1>;
80-
channel = <5>;
81-
renesas,sample-clock-div = <64>;
82-
#port-irq-cells = <0>;
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status = "disabled";
84-
};
85-
86-
port_irq8: external-interrupt@40006008 {
87-
compatible = "renesas,ra-external-interrupt";
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reg = <0x40006008 0x1>;
89-
channel = <8>;
90-
renesas,sample-clock-div = <64>;
91-
#port-irq-cells = <0>;
92-
status = "disabled";
93-
};
94-
95-
port_irq10: external-interrupt@4000600a {
96-
compatible = "renesas,ra-external-interrupt";
97-
reg = <0x4000600a 0x1>;
98-
channel = <10>;
99-
renesas,sample-clock-div = <64>;
100-
#port-irq-cells = <0>;
101-
status = "disabled";
102-
};
103-
104-
port_irq12: external-interrupt@4000600c {
105-
compatible = "renesas,ra-external-interrupt";
106-
reg = <0x4000600c 0x1>;
107-
channel = <12>;
108-
renesas,sample-clock-div = <64>;
109-
#port-irq-cells = <0>;
110-
status = "disabled";
111-
};
112-
113-
trng: trng {
114-
compatible = "renesas,ra-sce5-rng";
115-
status = "disabled";
116-
};
117-
118-
pwm6: pwm6@40078600 {
119-
compatible = "renesas,ra-pwm";
120-
divider = <RA_PWM_SOURCE_DIV_1>;
121-
channel = <RA_PWM_CHANNEL_6>;
122-
clocks = <&pclkd MSTPD 6>;
123-
reg = <0x40078600 0x100>;
124-
#pwm-cells = <3>;
125-
status = "disabled";
126-
};
127-
128-
pwm7: pwm7@40078700 {
129-
compatible = "renesas,ra-pwm";
130-
divider = <RA_PWM_SOURCE_DIV_1>;
131-
channel = <RA_PWM_CHANNEL_7>;
132-
clocks = <&pclkd MSTPD 6>;
133-
reg = <0x40078700 0x100>;
134-
#pwm-cells = <3>;
135-
status = "disabled";
136-
};
137-
};
138-
139-
clocks: clocks {
140-
#address-cells = <1>;
141-
#size-cells = <1>;
142-
143-
xtal: clock-main-osc {
144-
compatible = "renesas,ra-cgc-external-clock";
145-
clock-frequency = <DT_FREQ_M(12)>;
146-
#clock-cells = <0>;
147-
status = "disabled";
148-
};
149-
150-
hoco: clock-hoco {
151-
compatible = "fixed-clock";
152-
clock-frequency = <DT_FREQ_M(24)>;
153-
#clock-cells = <0>;
154-
};
155-
156-
moco: clock-moco {
157-
compatible = "fixed-clock";
158-
clock-frequency = <DT_FREQ_M(8)>;
159-
#clock-cells = <0>;
160-
};
161-
162-
loco: clock-loco {
163-
compatible = "fixed-clock";
164-
clock-frequency = <32768>;
165-
#clock-cells = <0>;
166-
};
167-
168-
subclk: clock-subclk {
169-
compatible = "renesas,ra-cgc-subclk";
170-
clock-frequency = <32768>;
171-
#clock-cells = <0>;
172-
status = "disabled";
173-
};
174-
175-
pll: pll {
176-
compatible = "renesas,ra-cgc-pll";
177-
#clock-cells = <0>;
178-
179-
clocks = <&xtal>;
180-
div = <2>;
181-
mul = <8 0>;
182-
status = "disabled";
183-
};
184-
185-
pclkblock: pclkblock@40047000 {
186-
compatible = "renesas,ra-cgc-pclk-block";
187-
reg = <0x40047000 4>,
188-
<0x40047004 4>,
189-
<0x40047008 4>;
190-
reg-names = "MSTPB", "MSTPC", "MSTPD";
191-
#clock-cells = <0>;
192-
clocks = <&pll>;
193-
status = "okay";
194-
195-
iclk: iclk {
196-
compatible = "renesas,ra-cgc-pclk";
197-
clock-frequency = <48000000>;
198-
div = <1>;
199-
#clock-cells = <2>;
200-
status = "okay";
201-
};
202-
203-
pclka: pclka {
204-
compatible = "renesas,ra-cgc-pclk";
205-
div = <1>;
206-
#clock-cells = <2>;
207-
status = "okay";
208-
};
209-
210-
pclkb: pclkb {
211-
compatible = "renesas,ra-cgc-pclk";
212-
div = <2>;
213-
#clock-cells = <2>;
214-
status = "okay";
215-
};
216-
217-
pclkc: pclkc {
218-
compatible = "renesas,ra-cgc-pclk";
219-
div = <1>;
220-
#clock-cells = <2>;
221-
status = "okay";
222-
};
223-
224-
pclkd: pclkd {
225-
compatible = "renesas,ra-cgc-pclk";
226-
div = <1>;
227-
#clock-cells = <2>;
228-
status = "okay";
229-
};
230-
231-
fclk: fclk {
232-
compatible = "renesas,ra-cgc-pclk";
233-
div = <2>;
234-
#clock-cells = <2>;
235-
status = "okay";
236-
};
237-
238-
clkout: clkout {
239-
compatible = "renesas,ra-cgc-pclk";
240-
#clock-cells = <2>;
241-
status = "disabled";
242-
};
243-
244-
uclk: uclk {
245-
compatible = "renesas,ra-cgc-pclk";
246-
#clock-cells = <2>;
247-
status = "disabled";
248-
};
249-
};
250-
};
251-
};
252-
253-
&ioport0 {
254-
port-irqs = <&port_irq2 &port_irq3 &port_irq6
255-
&port_irq7 &port_irq10 &port_irq15>;
256-
port-irq-names = "port-irq2",
257-
"port-irq3",
258-
"port-irq6",
259-
"port-irq7",
260-
"port-irq10",
261-
"port-irq15";
262-
port-irq2-pins = <2>;
263-
port-irq3-pins = <4>;
264-
port-irq6-pins = <0>;
265-
port-irq7-pins = <1 15>;
266-
port-irq10-pins = <5>;
267-
port-irq15-pins = <11>;
268-
};
269-
270-
&ioport1 {
271-
port-irqs = <&port_irq0 &port_irq1 &port_irq2
272-
&port_irq3 &port_irq4>;
273-
port-irq-names = "port-irq0",
274-
"port-irq1",
275-
"port-irq2",
276-
"port-irq3",
277-
"port-irq4";
278-
port-irq0-pins = <5>;
279-
port-irq1-pins = <1 4>;
280-
port-irq2-pins = <0>;
281-
port-irq3-pins = <10>;
282-
port-irq4-pins = <11>;
283-
};
284-
285-
&ioport2 {
286-
port-irqs = <&port_irq0 &port_irq1 &port_irq2
287-
&port_irq3>;
288-
port-irq-names = "port-irq0",
289-
"port-irq1",
290-
"port-irq2",
291-
"port-irq3";
292-
port-irq0-pins = <6>;
293-
port-irq1-pins = <5>;
294-
port-irq2-pins = <13>;
295-
port-irq3-pins = <12>;
296-
};
297-
298-
&ioport3 {
299-
port-irqs = <&port_irq5 &port_irq6 &port_irq8
300-
&port_irq9>;
301-
port-irq-names = "port-irq5",
302-
"port-irq6",
303-
"port-irq8",
304-
"port-irq9";
305-
port-irq5-pins = <2>;
306-
port-irq6-pins = <1>;
307-
port-irq8-pins = <5>;
308-
port-irq9-pins = <4>;
309-
};
310-
311-
&ioport4 {
312-
port-irqs = <&port_irq0 &port_irq4 &port_irq5
313-
&port_irq6 &port_irq7 &port_irq8
314-
&port_irq9>;
315-
port-irq-names = "port-irq0",
316-
"port-irq4",
317-
"port-irq5",
318-
"port-irq6",
319-
"port-irq7",
320-
"port-irq8",
321-
"port-irq9";
322-
port-irq0-pins = <0>;
323-
port-irq4-pins = <2 11>;
324-
port-irq5-pins = <1 10>;
325-
port-irq6-pins = <9>;
326-
port-irq7-pins = <8>;
327-
port-irq8-pins = <15>;
328-
port-irq9-pins = <14>;
329-
};
330-
331-
&ioport5 {
332-
port-irqs = <&port_irq11 &port_irq12 &port_irq14>;
333-
port-irq-names = "port-irq11",
334-
"port-irq12",
335-
"port-irq14";
336-
port-irq11-pins = <1>;
337-
port-irq12-pins = <2>;
338-
port-irq14-pins = <5>;
339-
};
340-
341-
&pwm2 {
342-
clocks = <&pclkd MSTPD 6>;
343-
};
344-
345-
&pwm3 {
346-
clocks = <&pclkd MSTPD 6>;
11+
soc {
12+
flash-controller@407e0000 {
13+
flash0: flash@0 {
14+
compatible = "soc-nv-flash";
15+
reg = <0x0 DT_SIZE_K(256)>;
16+
};
17+
};
18+
};
34719
};

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