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mxrt685: Add USDHC support for RT685
Add USDHC support for RT685 Signed-off-by: Mahesh Mahadevan <[email protected]>
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‎boards/arm/mimxrt685_evk/Kconfig.defconfig‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,4 +38,7 @@ config HEAP_MEM_POOL_SIZE
3838

3939
endif # DMA_MCUX_LPC
4040

41+
config DISK_DRIVER_SDMMC
42+
default y if DISK_DRIVERS
43+
4144
endif # BOARD_MIMXRT685_EVK

‎boards/arm/mimxrt685_evk/doc/index.rst‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,8 @@ features:
9191
+-----------+------------+-------------------------------------+
9292
| WDT | on-chip | watchdog |
9393
+-----------+------------+-------------------------------------+
94+
| SDHC | on-chip | disk access |
95+
+-----------+------------+-------------------------------------+
9496

9597
The default configuration can be found in the defconfig file:
9698

@@ -165,6 +167,24 @@ functionality of a pin.
165167
+---------+-----------------+----------------------------+
166168
| PIO0_27 | SCT0_OUT7 | PWM |
167169
+---------+-----------------+----------------------------+
170+
| PIO1_30 | SD0_CLK | SD card |
171+
+---------+-----------------+----------------------------+
172+
| PIO1_31 | SD0_CMD | SD card |
173+
+---------+-----------------+----------------------------+
174+
| PIO2_0 | SD0_D0 | SD card |
175+
+---------+-----------------+----------------------------+
176+
| PIO2_1 | SD0_D1 | SD card |
177+
+---------+-----------------+----------------------------+
178+
| PIO2_2 | SD0_D2 | SD card |
179+
+---------+-----------------+----------------------------+
180+
| PIO2_3 | SD0_D3 | SD card |
181+
+---------+-----------------+----------------------------+
182+
| PIO2_4 | SD0_WR_PRT | SD card |
183+
+---------+-----------------+----------------------------+
184+
| PIO2_9 | SD0_CD | SD card |
185+
+---------+-----------------+----------------------------+
186+
| PIO2_10 | SD0_RST | SD card |
187+
+---------+-----------------+----------------------------+
168188

169189
System Clock
170190
============

‎boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -253,6 +253,10 @@ i2s1: &flexcomm3 {
253253
status = "okay";
254254
};
255255

256+
&gpio2 {
257+
status = "okay";
258+
};
259+
256260
&dma0 {
257261
/*
258262
* The total number of dma channels available is defined by
@@ -293,3 +297,8 @@ i2s1: &flexcomm3 {
293297
&sc_timer {
294298
status = "okay";
295299
};
300+
301+
&usdhc1 {
302+
status = "okay";
303+
pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
304+
};

‎boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,5 +25,6 @@ supported:
2525
- hwinfo
2626
- i2c
2727
- i2s
28+
- sdhc
2829
- spi
2930
- watchdog

‎boards/arm/mimxrt685_evk/pinmux.c‎

Lines changed: 191 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -768,6 +768,197 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev)
768768
IOPCTL_PinMuxSet(IOPCTL, 0U, 31U, port0_pin31_config);
769769
#endif
770770

771+
#endif
772+
773+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
774+
uint32_t port1_pin30_config = (/* Pin is configured as SD0_CLK */
775+
IOPCTL_PIO_FUNC1 |
776+
/* Disable pull-up / pull-down function */
777+
IOPCTL_PIO_PUPD_DI |
778+
/* Enable pull-down function */
779+
IOPCTL_PIO_PULLDOWN_EN |
780+
/* Enables input buffer function */
781+
IOPCTL_PIO_INBUF_EN |
782+
/* Normal mode */
783+
IOPCTL_PIO_SLEW_RATE_NORMAL |
784+
/* Normal drive */
785+
IOPCTL_PIO_FULLDRIVE_DI |
786+
/* Analog mux is disabled */
787+
IOPCTL_PIO_ANAMUX_DI |
788+
/* Pseudo Output Drain is disabled */
789+
IOPCTL_PIO_PSEDRAIN_DI |
790+
/* Input function is not inverted */
791+
IOPCTL_PIO_INV_DI);
792+
/* PORT1 PIN30 (coords: P10) is configured as SD0_CLK */
793+
IOPCTL_PinMuxSet(IOPCTL, 1U, 30U, port1_pin30_config);
794+
795+
uint32_t port1_pin31_config = (/* Pin is configured as SD0_CMD */
796+
IOPCTL_PIO_FUNC1 |
797+
/* Enable pull-up / pull-down function */
798+
IOPCTL_PIO_PUPD_EN |
799+
/* Enable pull-up function */
800+
IOPCTL_PIO_PULLUP_EN |
801+
/* Enables input buffer function */
802+
IOPCTL_PIO_INBUF_EN |
803+
/* Normal mode */
804+
IOPCTL_PIO_SLEW_RATE_NORMAL |
805+
/* Normal drive */
806+
IOPCTL_PIO_FULLDRIVE_DI |
807+
/* Analog mux is disabled */
808+
IOPCTL_PIO_ANAMUX_DI |
809+
/* Pseudo Output Drain is disabled */
810+
IOPCTL_PIO_PSEDRAIN_DI |
811+
/* Input function is not inverted */
812+
IOPCTL_PIO_INV_DI);
813+
/* PORT1 PIN31 (coords: R9) is configured as SD0_CMD */
814+
IOPCTL_PinMuxSet(IOPCTL, 1U, 31U, port1_pin31_config);
815+
816+
uint32_t port2_pin0_config = (/* Pin is configured as SD0_D0 */
817+
IOPCTL_PIO_FUNC1 |
818+
/* Enable pull-up / pull-down function */
819+
IOPCTL_PIO_PUPD_EN |
820+
/* Enable pull-up function */
821+
IOPCTL_PIO_PULLUP_EN |
822+
/* Enables input buffer function */
823+
IOPCTL_PIO_INBUF_EN |
824+
/* Normal mode */
825+
IOPCTL_PIO_SLEW_RATE_NORMAL |
826+
/* Normal drive */
827+
IOPCTL_PIO_FULLDRIVE_DI |
828+
/* Analog mux is disabled */
829+
IOPCTL_PIO_ANAMUX_DI |
830+
/* Pseudo Output Drain is disabled */
831+
IOPCTL_PIO_PSEDRAIN_DI |
832+
/* Input function is not inverted */
833+
IOPCTL_PIO_INV_DI);
834+
/* PORT2 PIN0 (coords: R11) is configured as SD0_D0 */
835+
IOPCTL_PinMuxSet(IOPCTL, 2U, 0U, port2_pin0_config);
836+
837+
uint32_t port2_pin1_config = (/* Pin is configured as SD0_D1 */
838+
IOPCTL_PIO_FUNC1 |
839+
/* Enable pull-up / pull-down function */
840+
IOPCTL_PIO_PUPD_EN |
841+
/* Enable pull-up function */
842+
IOPCTL_PIO_PULLUP_EN |
843+
/* Enables input buffer function */
844+
IOPCTL_PIO_INBUF_EN |
845+
/* Normal mode */
846+
IOPCTL_PIO_SLEW_RATE_NORMAL |
847+
/* Normal drive */
848+
IOPCTL_PIO_FULLDRIVE_DI |
849+
/* Analog mux is disabled */
850+
IOPCTL_PIO_ANAMUX_DI |
851+
/* Pseudo Output Drain is disabled */
852+
IOPCTL_PIO_PSEDRAIN_DI |
853+
/* Input function is not inverted */
854+
IOPCTL_PIO_INV_DI);
855+
/* PORT2 PIN1 (coords: T11) is configured as SD0_D1 */
856+
IOPCTL_PinMuxSet(IOPCTL, 2U, 1U, port2_pin1_config);
857+
858+
uint32_t port2_pin10_config = (/* Pin is configured as PIO2_10 */
859+
IOPCTL_PIO_FUNC0 |
860+
/* Disable pull-up / pull-down function */
861+
IOPCTL_PIO_PUPD_DI |
862+
/* Enable pull-down function */
863+
IOPCTL_PIO_PULLDOWN_EN |
864+
/* Disable input buffer function */
865+
IOPCTL_PIO_INBUF_DI |
866+
/* Normal mode */
867+
IOPCTL_PIO_SLEW_RATE_NORMAL |
868+
/* Normal drive */
869+
IOPCTL_PIO_FULLDRIVE_DI |
870+
/* Analog mux is disabled */
871+
IOPCTL_PIO_ANAMUX_DI |
872+
/* Pseudo Output Drain is disabled */
873+
IOPCTL_PIO_PSEDRAIN_DI |
874+
/* Input function is not inverted */
875+
IOPCTL_PIO_INV_DI);
876+
/* PORT2 PIN10 (coords: T15) is configured as PIO2_10 */
877+
IOPCTL_PinMuxSet(IOPCTL, 2U, 10U, port2_pin10_config);
878+
879+
uint32_t port2_pin2_config = (/* Pin is configured as SD0_D2 */
880+
IOPCTL_PIO_FUNC1 |
881+
/* Enable pull-up / pull-down function */
882+
IOPCTL_PIO_PUPD_EN |
883+
/* Enable pull-up function */
884+
IOPCTL_PIO_PULLUP_EN |
885+
/* Enables input buffer function */
886+
IOPCTL_PIO_INBUF_EN |
887+
/* Normal mode */
888+
IOPCTL_PIO_SLEW_RATE_NORMAL |
889+
/* Normal drive */
890+
IOPCTL_PIO_FULLDRIVE_DI |
891+
/* Analog mux is disabled */
892+
IOPCTL_PIO_ANAMUX_DI |
893+
/* Pseudo Output Drain is disabled */
894+
IOPCTL_PIO_PSEDRAIN_DI |
895+
/* Input function is not inverted */
896+
IOPCTL_PIO_INV_DI);
897+
/* PORT2 PIN2 (coords: U11) is configured as SD0_D2 */
898+
IOPCTL_PinMuxSet(IOPCTL, 2U, 2U, port2_pin2_config);
899+
900+
uint32_t port2_pin3_config = (/* Pin is configured as SD0_D3 */
901+
IOPCTL_PIO_FUNC1 |
902+
/* Enable pull-up / pull-down function */
903+
IOPCTL_PIO_PUPD_EN |
904+
/* Enable pull-up function */
905+
IOPCTL_PIO_PULLUP_EN |
906+
/* Enables input buffer function */
907+
IOPCTL_PIO_INBUF_EN |
908+
/* Normal mode */
909+
IOPCTL_PIO_SLEW_RATE_NORMAL |
910+
/* Normal drive */
911+
IOPCTL_PIO_FULLDRIVE_DI |
912+
/* Analog mux is disabled */
913+
IOPCTL_PIO_ANAMUX_DI |
914+
/* Pseudo Output Drain is disabled */
915+
IOPCTL_PIO_PSEDRAIN_DI |
916+
/* Input function is not inverted */
917+
IOPCTL_PIO_INV_DI);
918+
/* PORT2 PIN3 (coords: T12) is configured as SD0_D3 */
919+
IOPCTL_PinMuxSet(IOPCTL, 2U, 3U, port2_pin3_config);
920+
921+
uint32_t port2_pin4_config = (/* Pin is configured as PIO2_4 */
922+
IOPCTL_PIO_FUNC0 |
923+
/* Disable pull-up / pull-down function */
924+
IOPCTL_PIO_PUPD_DI |
925+
/* Enable pull-down function */
926+
IOPCTL_PIO_PULLDOWN_EN |
927+
/* Disable input buffer function */
928+
IOPCTL_PIO_INBUF_DI |
929+
/* Normal mode */
930+
IOPCTL_PIO_SLEW_RATE_NORMAL |
931+
/* Normal drive */
932+
IOPCTL_PIO_FULLDRIVE_DI |
933+
/* Analog mux is disabled */
934+
IOPCTL_PIO_ANAMUX_DI |
935+
/* Pseudo Output Drain is disabled */
936+
IOPCTL_PIO_PSEDRAIN_DI |
937+
/* Input function is not inverted */
938+
IOPCTL_PIO_INV_DI);
939+
/* PORT2 PIN4 (coords: T13) is configured as PIO2_4 */
940+
IOPCTL_PinMuxSet(IOPCTL, 2U, 4U, port2_pin4_config);
941+
942+
uint32_t port2_pin9_config = (/* Pin is configured as SD0_CARD_DET_N */
943+
IOPCTL_PIO_FUNC1 |
944+
/* Enable pull-up / pull-down function */
945+
IOPCTL_PIO_PUPD_EN |
946+
/* Enable pull-up function */
947+
IOPCTL_PIO_PULLUP_EN |
948+
/* Enables input buffer function */
949+
IOPCTL_PIO_INBUF_EN |
950+
/* Normal mode */
951+
IOPCTL_PIO_SLEW_RATE_NORMAL |
952+
/* Normal drive */
953+
IOPCTL_PIO_FULLDRIVE_DI |
954+
/* Analog mux is disabled */
955+
IOPCTL_PIO_ANAMUX_DI |
956+
/* Pseudo Output Drain is disabled */
957+
IOPCTL_PIO_PSEDRAIN_DI |
958+
/* Input function is not inverted */
959+
IOPCTL_PIO_INV_DI);
960+
/* PORT2 PIN9 (coords: R13) is configured as SD0_CARD_DET_N */
961+
IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config);
771962
#endif
772963

773964
return 0;

‎dts/arm/nxp/nxp_rt6xx_common.dtsi‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -277,6 +277,24 @@
277277
clk-divider = <1>;
278278
label = "WWDT_1";
279279
};
280+
281+
usdhc1: usdhc@136000 {
282+
compatible = "nxp,imx-usdhc";
283+
reg = <0x136000 0x4000>;
284+
status = "disabled";
285+
interrupts = <45 0>;
286+
clocks = <&clkctl1 MCUX_USDHC1_CLK>;
287+
label = "USDHC_1";
288+
};
289+
290+
usdhc2: usdhc@137000 {
291+
compatible = "nxp,imx-usdhc";
292+
reg = <0x137000 0x4000>;
293+
status = "disabled";
294+
interrupts = <46 0>;
295+
clocks = <&clkctl1 MCUX_USDHC2_CLK>;
296+
label = "USDHC_2";
297+
};
280298
};
281299

282300
&nvic {

‎soc/arm/nxp_imx/rt6xx/Kconfig.soc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@ config SOC_MIMXRT685S_CM33
2525
select HAS_MCUX_LPC_RTC
2626
select HAS_MCUX_TRNG
2727
select HAS_MCUX_SCTIMER
28+
select HAS_MCUX_USDHC1
29+
select HAS_MCUX_USDHC2
2830
select INIT_SYS_PLL
2931

3032
endchoice

‎soc/arm/nxp_imx/rt6xx/soc.c‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,7 @@ static ALWAYS_INLINE void clock_init(void)
171171
/* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */
172172
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3);
173173
#endif
174+
174175
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay))
175176
CLOCK_AttachClk(kLPOSC_to_WDT0_CLK);
176177
#else
@@ -179,9 +180,34 @@ static ALWAYS_INLINE void clock_init(void)
179180
*/
180181
CLOCK_AttachClk(kNONE_to_WDT0_CLK);
181182
#endif
183+
184+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
185+
/* Make sure USDHC ram buffer has been power up*/
186+
POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM);
187+
POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM);
188+
POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
189+
POWER_ApplyPD();
190+
191+
/* usdhc depend on 32K clock also */
192+
CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK);
193+
CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK);
194+
CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1);
195+
CLOCK_EnableClock(kCLOCK_Sdio0);
196+
RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn);
197+
#endif
198+
182199
#endif /* CONFIG_SOC_MIMXRT685S_CM33 */
183200
}
184201

202+
#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC)
203+
204+
void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init,
205+
uint32_t speed, uint32_t strength)
206+
{
207+
208+
}
209+
#endif
210+
185211
/**
186212
*
187213
* @brief Perform basic hardware initialization

‎soc/arm/nxp_imx/rt6xx/soc.h‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,4 +75,21 @@
7575
/*!<@brief Slow mode */
7676
#define IOPCTL_PIO_SLEW_RATE_SLOW 0x80u
7777

78+
#ifdef __cplusplus
79+
extern "C" {
80+
#endif
81+
82+
#if CONFIG_DISK_DRIVER_SDMMC && \
83+
(DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) || \
84+
DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay))
85+
86+
void imxrt_usdhc_pinmux(uint16_t nusdhc,
87+
bool init, uint32_t speed, uint32_t strength);
88+
89+
#endif
90+
91+
#ifdef __cplusplus
92+
}
93+
#endif
94+
7895
#endif /* _SOC__H_ */

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