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tests: boards: espressif: Nested IRQ
Add test suite to test nested interrupts on ESP32 Xtensa targets. Signed-off-by: Marek Matej <[email protected]>
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‎tests/boards/espressif/interrupt/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(esp_interrupt_test)
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target_sources(app PRIVATE src/main.c)

‎tests/boards/espressif/interrupt/README.rst‎

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.. _interrupt_test:
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Espressif's Xtensa interrupt test
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#################################
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Overview
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********
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Test objective is to verify that the ESP32, ESP32-S2 and ESP32-S3 platforms correctly support nested interrupts, where higher-priority interrupts can preempt lower-priority ones.
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Three independent hardware timers are configured.
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Each timer is assigned an ISR (Interrupt Service Routine) with a priority one level higher than the previous timer.
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* Timer 1: lowest priority ISR
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* Timer 2: medium priority ISR
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* Timer 3: highest priority ISR
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Execution Flow
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--------------
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* Timer 1 ISR triggers first. - It simulates work (waits briefly).
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* Before completing, it triggers Timer 2 interrupt.
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* Timer 2 ISR preempts Timer 1 ISR (because of higher priority). - It also simulates work.
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* It triggers Timer 3 interrupt.
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* Timer 3 ISR preempts Timer 2 ISR (highest priority). - It performs its work and completes execution.
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* After Timer 3 ISR completes, control returns to Timer 2 ISR, which then completes.
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* Finally, execution resumes and completes Timer 1 ISR.
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Success Criteria
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----------------
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Each ISR execution is verified by setting a unique "magic value". The test is successful if:
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* Timer 1 ISR sets its magic value.
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* Timer 2 ISR sets its magic value.
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* Timer 3 ISR sets its magic value.
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This confirms that ISR priorities are respected and preemption works correctly.
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Supported Boards
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****************
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- esp32_devkitc/esp32/procpu
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- esp32s2_saola
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- esp32s3_devkitm/esp32s3/procpu
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Building and Running
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********************
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Make sure you have the target connected over USB port.
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.. code-block:: console
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west build -b <board> tests/boards/espressif/interrupt
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west flash && west espressif monitor
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To run the test with twister, use the following command:
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.. code-block:: console
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west twister -p <board> --device-testing --device-serial=/dev/ttyUSB0 -vv --flash-before -T tests/boards/espressif/interrupt
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If the external 32K crystal is connect to pins 32K_XP and 32K_XN, the test can be run with ``external_xtal`` fixture enabled:
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.. code-block:: console
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west twister -p esp32s3_devkitm --device-testing --device-serial=/dev/ttyUSB0 -vv --flash-before -T tests/boards/espressif/interrupt
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Sample Output
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=============
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.. code-block:: console
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*** Booting Zephyr OS build v4.2.0-2885-g158729997aec ***
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Running TESTSUITE esp_interrupt
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===================================================================
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START - test_nested_isr
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PASS - test_nested_isr in 10.101 seconds
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===================================================================
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TESTSUITE esp_interrupt succeeded
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------ TESTSUITE SUMMARY START ------
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SUITE PASS - 100.00% [esp_interrupt]: pass = 1, fail = 0, skip = 0, total = 1 duration = 10.101 seconds
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- PASS - [esp_interrupt.test_nested_isr] duration = 10.101 seconds
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------ TESTSUITE SUMMARY END ------
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===================================================================
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PROJECT EXECUTION SUCCESSFUL

‎tests/boards/espressif/interrupt/prj.conf‎

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CONFIG_ZTEST=y
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CONFIG_COUNTER=y

‎tests/boards/espressif/interrupt/socs/esp32_procpu.overlay‎

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&timer0 {
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status = "okay";
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interrupts = <TG0_T0_LEVEL_INTR_SOURCE 1 0>;
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counter {
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status = "okay";
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};
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};
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&timer1 {
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status = "okay";
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interrupts = <TG0_T1_LEVEL_INTR_SOURCE 2 0>;
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counter {
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status = "okay";
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};
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};
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&timer2 {
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status = "okay";
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interrupts = <TG1_T0_LEVEL_INTR_SOURCE 3 0>;
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counter {
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status = "okay";
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};
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};

‎tests/boards/espressif/interrupt/socs/esp32s2.overlay‎

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&timer0 {
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status = "okay";
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interrupts = <TG0_T0_LEVEL_INTR_SOURCE 1 0>;
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counter {
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status = "okay";
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};
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};
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&timer1 {
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status = "okay";
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interrupts = <TG0_T1_LEVEL_INTR_SOURCE 2 0>;
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counter {
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status = "okay";
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};
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};
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&timer2 {
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status = "okay";
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interrupts = <TG1_T0_LEVEL_INTR_SOURCE 3 0>;
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counter {
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status = "okay";
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};
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};

‎tests/boards/espressif/interrupt/socs/esp32s3_procpu.overlay‎

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&timer0 {
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status = "okay";
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interrupts = <TG0_T0_LEVEL_INTR_SOURCE 1 0>;
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counter {
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status = "okay";
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};
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};
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&timer1 {
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status = "okay";
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interrupts = <TG0_T1_LEVEL_INTR_SOURCE 2 0>;
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counter {
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status = "okay";
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};
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};
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&timer2 {
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status = "okay";
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interrupts = <TG1_T0_LEVEL_INTR_SOURCE 3 0>;
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counter {
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status = "okay";
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};
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};

‎tests/boards/espressif/interrupt/src/main.c‎

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/ztest.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/sys/printk.h>
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/* Test sets the three timer units, each with different interrupt priority level.
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* Each timer/counter is set to respond to three separate alarms.
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* The alarm times are set so each would trigger one after another separated by
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* the `ALARM_DIFF_US` time.
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* Each ISR sets its corresponding token into its token slots and wait for the
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* subsequent alarm ISR to be called.
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* After the last alarm ISR finishes the main loop checks if the ISR were called.
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*/
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#define TOKEN_A 0xBEEFBABE
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#define TOKEN_B 0xC0FEB00B
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#define TOKEN_C 0xDEAD5AA5
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#define ALARM_DIFF_US 1000
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#define ALARM_A_US (1000 + ALARM_DIFF_US)
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#define ALARM_B_US (ALARM_A_US + ALARM_DIFF_US)
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#define ALARM_C_US (ALARM_B_US + ALARM_DIFF_US)
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#define ISR_DELAY_US (ALARM_DIFF_US * 3)
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#define CYCLE_MS 10
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#define TEST_CYCLES 1000
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static const struct device *const timer0 = DEVICE_DT_GET(DT_INST(0, espressif_esp32_counter));
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static const struct device *const timer1 = DEVICE_DT_GET(DT_INST(1, espressif_esp32_counter));
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static const struct device *const timer2 = DEVICE_DT_GET(DT_INST(2, espressif_esp32_counter));
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static struct counter_alarm_cfg alarm_a;
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static struct counter_alarm_cfg alarm_b;
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static struct counter_alarm_cfg alarm_c;
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static int token[3];
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static int success_cnt;
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static int error_cnt;
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static void alarm_handler_c(const struct device *dev, uint8_t chan_id, uint32_t counter,
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void *user_data)
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{
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if (dev == timer2 && token[0] == TOKEN_A && token[1] == TOKEN_B && token[2] == 0) {
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token[2] = TOKEN_C;
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}
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k_busy_wait(ISR_DELAY_US);
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}
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static void alarm_handler_b(const struct device *dev, uint8_t chan_id, uint32_t counter,
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void *user_data)
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{
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if (dev == timer1 && token[0] == TOKEN_A && token[1] == 0 && token[2] == 0) {
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token[1] = TOKEN_B;
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}
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k_busy_wait(ISR_DELAY_US);
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}
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static void alarm_handler_a(const struct device *dev, uint8_t chan_id, uint32_t counter,
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void *user_data)
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{
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if (dev == timer0 && token[0] == 0 && token[1] == 0 && token[2] == 0) {
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token[0] = TOKEN_A;
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}
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k_busy_wait(ISR_DELAY_US);
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}
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static void *esp_interrupt_suite_setup(void)
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{
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zassert_true(device_is_ready(timer0), "Device %s not ready", timer0->name);
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zassert_true(device_is_ready(timer1), "Device %s not ready", timer1->name);
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zassert_true(device_is_ready(timer2), "Device %s not ready", timer2->name);
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zassert_false(counter_start(timer0), "Timer 0 failed to start");
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zassert_false(counter_start(timer1), "Timer 1 failed to start");
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zassert_false(counter_start(timer2), "Timer 2 failed to start");
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return NULL;
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}
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ZTEST(esp_interrupt, test_nested_isr)
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{
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uint32_t cnt = TEST_CYCLES;
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success_cnt = 0;
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error_cnt = 0;
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while (cnt--) {
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alarm_a.ticks = counter_us_to_ticks(timer0, ALARM_A_US);
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alarm_a.callback = alarm_handler_a;
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alarm_b.ticks = counter_us_to_ticks(timer1, ALARM_B_US);
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alarm_b.callback = alarm_handler_b;
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alarm_c.ticks = counter_us_to_ticks(timer2, ALARM_C_US);
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alarm_c.callback = alarm_handler_c;
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counter_reset(timer0);
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counter_reset(timer1);
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counter_reset(timer2);
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zassert_false(counter_set_channel_alarm(timer0, 0, &alarm_a),
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"Failed to set alarm A");
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zassert_false(counter_set_channel_alarm(timer1, 0, &alarm_b),
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"Failed to set alarm B");
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zassert_false(counter_set_channel_alarm(timer2, 0, &alarm_c),
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"Failed to set alarm C");
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k_msleep(CYCLE_MS);
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if (token[0] == TOKEN_A && token[1] == TOKEN_B && token[2] == TOKEN_C) {
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success_cnt++;
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} else {
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error_cnt++;
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}
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token[0] = 0;
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token[1] = 0;
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token[2] = 0;
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}
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zassert_true(error_cnt == 0, "Errors occurred (%d)", error_cnt);
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zassert_true(success_cnt == TEST_CYCLES, "Not all test cycles pssed (%d from %d)",
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success_cnt, TEST_CYCLES);
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}
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ZTEST_SUITE(esp_interrupt, NULL, esp_interrupt_suite_setup, NULL, NULL, NULL);

‎tests/boards/espressif/interrupt/testcase.yaml‎

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common:
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integration_platforms:
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- esp32s3_devkitm/esp32s3/procpu
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tests:
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boards.esp32.interrupts:
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tags:
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- drivers
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platform_allow:
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- esp32_devkitc/esp32/procpu
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- esp32s2_saola
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- esp32s3_devkitm/esp32s3/procpu

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