soc: mspm0: Add a support for TI MSPM0-G series SoC

Add a support for Texas Instruments MSPM0 fmaily and
MSPM0-G series SoC.

Signed-off-by: Saravanan Sekar <[email protected]>
Signed-off-by: Jackson Farley <[email protected]>

Author: ssekar15

modules/Kconfig

@@ -29,6 +29,7 @@ source "modules/Kconfig.infineon"
 source "modules/Kconfig.libmetal"
 source "modules/lvgl/Kconfig"
 source "modules/Kconfig.microchip"
+source "modules/Kconfig.mspm0"
 source "modules/Kconfig.nuvoton"
 source "modules/Kconfig.open-amp"
 source "modules/Kconfig.picolibc"

modules/Kconfig.mspm0

@@ -0,0 +1,13 @@
+# MSPM0 SDK configuration
+
+# Copyright (c) 2025 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+config HAS_MSPM0_SDK
+	bool
+
+config USE_MSPM0_DL_GPIO
+	bool
+
+config USE_MSPM0_DL_UART
+	bool

soc/ti/mspm0/CMakeLists.txt

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker Script")
+
+add_subdirectory(${SOC_SERIES})
+
+if(CONFIG_SOC_FAMILY_TI_MSPM0)
+	string(TOUPPER ${CONFIG_SOC} SDK_SOC_SELECT)
+	zephyr_compile_definitions(-D__${SDK_SOC_SELECT}__)
+endif()

soc/ti/mspm0/Kconfig

@@ -0,0 +1,18 @@
+# Texas Instruments MSPM0 Family
+# Copyright (c) 2025 Texas Instruments
+# Copyright (c) 2025 Linumiz
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_TI_MSPM0
+
+rsource "*/Kconfig"
+
+# Per TRM Section 2.2.7 Peripheral Power Enable Control: wait at least 4 ULPCLK
+# clock cycles before accessing the peripheral's memory-mapped registers.
+# ULPCLK will either be equivalent or half of the main MCLK and CPUCLK,
+# yielding the delay time of 8 cycles
+config MSPM0_PERIPH_STARTUP_DELAY
+	int
+	default 8
+
+endif # SOC_FAMILY_TI_MSPM0

soc/ti/mspm0/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2025 Texas Instruments
+# Copyright (c) 2025 Linumiz
+
+if SOC_FAMILY_TI_MSPM0
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_TI_MSPM0

soc/ti/mspm0/Kconfig.soc

@@ -0,0 +1,13 @@
+# Texas Instruments MSPM0 Family
+
+# Copyright (c) 2025 Texas Instruments
+# Copyright (c) 2025 Linumiz
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_TI_MSPM0
+	bool
+
+config SOC_FAMILY
+	default "ti_mspm0" if SOC_FAMILY_TI_MSPM0
+
+rsource "*/Kconfig.soc"

soc/ti/mspm0/mspm0g/CMakeLists.txt

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+zephyr_include_directories(.)

soc/ti/mspm0/mspm0g/Kconfig

@@ -0,0 +1,17 @@
+# TI MSPM0G
+
+# Copyright (c) 2025 Texas Instruments
+# Copyright (c) 2025 Linumiz
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MSPM0G
+	select ARM
+	select CPU_CORTEX_M0PLUS
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select BUILD_OUTPUT_BIN
+	select BUILD_OUTPUT_HEX
+	select HAS_MSPM0_SDK
+	select CLOCK_CONTROL
+	select SOC_EARLY_INIT_HOOK

soc/ti/mspm0/mspm0g/Kconfig.defconfig

@@ -0,0 +1,20 @@
+# TI MSPM0G series
+
+# Copyright (c) 2025 Texas Instruments
+# Copyright (c) 2025 Linumiz
+# SPDX-License-Identifier: Apache-2.0
+
+DT_CHOSEN_Z_FLASH := zephyr,flash
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+if SOC_SERIES_MSPM0G
+
+config NUM_IRQS
+	default 32
+
+endif # SOC_SERIES_MSPM0G

soc/ti/mspm0/mspm0g/Kconfig.soc

@@ -0,0 +1,84 @@
+# Copyright (c) 2024 Texas Instruments
+# Copyright (c) 2025 Linumiz
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MSPM0G
+	bool
+	select SOC_FAMILY_TI_MSPM0
+	help
+	  Enable support for TI MSPM0G series SoCs
+
+config SOC_MSPM0G1105
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G1106
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G1107
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G1505
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G1506
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G1507
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G1519
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G3105
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G3106
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G3107
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G3505
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G3506
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G3507
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_MSPM0G3519
+	bool
+	select SOC_SERIES_MSPM0G
+
+config SOC_SERIES
+	default "mspm0g" if SOC_SERIES_MSPM0G
+
+config SOC
+	default "mspm0g1105" if SOC_MSPM0G1105
+	default "mspm0g1106" if SOC_MSPM0G1106
+	default "mspm0g1107" if SOC_MSPM0G1107
+	default "mspm0g1505" if SOC_MSPM0G1505
+	default "mspm0g1506" if SOC_MSPM0G1506
+	default "mspm0g1507" if SOC_MSPM0G1507
+	default "mspm0g1519" if SOC_MSPM0G1519
+	default "mspm0g3105" if SOC_MSPM0G3105
+	default "mspm0g3106" if SOC_MSPM0G3106
+	default "mspm0g3107" if SOC_MSPM0G3107
+	default "mspm0g3505" if SOC_MSPM0G3505
+	default "mspm0g3506" if SOC_MSPM0G3506
+	default "mspm0g3507" if SOC_MSPM0G3507
+	default "mspm0g3519" if SOC_MSPM0G3519