drivers: clock_control: stm32: enable PLL1FRACN setting

Enables the fractional-N (FRACN) setting for PLL1 in the STM32H5XX
clock driver.
This feature allows achieving a system clock frequency of 250 MHz from
an 8 MHz `clk_hse`.

Signed-off-by: Pisit Sawangvonganan <[email protected]>

Author: ndrs-pst

drivers/clock_control/clock_stm32_ll_h5.c

@@ -478,6 +478,10 @@ static int set_up_plls(void)
 	LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
 
 	LL_RCC_PLL1FRACN_Disable();
+	if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
+		LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
+		LL_RCC_PLL1FRACN_Enable();
+	}
 
 	if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
 		LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);