|
1255 | 1255 | status = "disabled"; |
1256 | 1256 | }; |
1257 | 1257 |
|
| 1258 | + psi5_0: psi5@401e0000 { |
| 1259 | + compatible = "nxp,s32-psi5"; |
| 1260 | + reg = <0x401e0000 0x1000>; |
| 1261 | + #address-cells = <1>; |
| 1262 | + #size-cells = <0>; |
| 1263 | + status = "disabled"; |
| 1264 | + |
| 1265 | + psi5_0_ch0: ch@0 { |
| 1266 | + compatible = "nxp,s32-psi5-channel"; |
| 1267 | + reg = <0>; |
| 1268 | + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1269 | + status = "disabled"; |
| 1270 | + }; |
| 1271 | + |
| 1272 | + psi5_0_ch1: ch@1 { |
| 1273 | + compatible = "nxp,s32-psi5-channel"; |
| 1274 | + reg = <1>; |
| 1275 | + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1276 | + status = "disabled"; |
| 1277 | + }; |
| 1278 | + |
| 1279 | + psi5_0_ch2: ch@2 { |
| 1280 | + compatible = "nxp,s32-psi5-channel"; |
| 1281 | + reg = <2>; |
| 1282 | + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1283 | + status = "disabled"; |
| 1284 | + }; |
| 1285 | + |
| 1286 | + psi5_0_ch3: ch@3 { |
| 1287 | + compatible = "nxp,s32-psi5-channel"; |
| 1288 | + reg = <3>; |
| 1289 | + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1290 | + status = "disabled"; |
| 1291 | + }; |
| 1292 | + }; |
| 1293 | + |
| 1294 | + psi5_1: psi5@421e0000 { |
| 1295 | + compatible = "nxp,s32-psi5"; |
| 1296 | + reg = <0x421e0000 0x1000>; |
| 1297 | + #address-cells = <1>; |
| 1298 | + #size-cells = <0>; |
| 1299 | + status = "disabled"; |
| 1300 | + |
| 1301 | + psi5_1_ch0: ch@0 { |
| 1302 | + compatible = "nxp,s32-psi5-channel"; |
| 1303 | + reg = <0>; |
| 1304 | + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1305 | + status = "disabled"; |
| 1306 | + }; |
| 1307 | + |
| 1308 | + psi5_1_ch1: ch@1 { |
| 1309 | + compatible = "nxp,s32-psi5-channel"; |
| 1310 | + reg = <1>; |
| 1311 | + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1312 | + status = "disabled"; |
| 1313 | + }; |
| 1314 | + |
| 1315 | + psi5_1_ch2: ch@2 { |
| 1316 | + compatible = "nxp,s32-psi5-channel"; |
| 1317 | + reg = <2>; |
| 1318 | + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1319 | + status = "disabled"; |
| 1320 | + }; |
| 1321 | + |
| 1322 | + psi5_1_ch3: ch@3 { |
| 1323 | + compatible = "nxp,s32-psi5-channel"; |
| 1324 | + reg = <3>; |
| 1325 | + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| 1326 | + status = "disabled"; |
| 1327 | + }; |
| 1328 | + }; |
1258 | 1329 | }; |
1259 | 1330 | }; |
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