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boards: s32z270: enable support psi5
enable support psi5 Signed-off-by: Cong Nguyen Huu <[email protected]>
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2 files changed

+72
-1
lines changed

2 files changed

+72
-1
lines changed

dts/arm/nxp/nxp_s32z27x_r52.dtsi

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@@ -1255,5 +1255,76 @@
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status = "disabled";
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};
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psi5_0: psi5@401e0000 {
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compatible = "nxp,s32-psi5";
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reg = <0x401e0000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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psi5_0_ch0: ch@0 {
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compatible = "nxp,s32-psi5-channel";
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reg = <0>;
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interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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psi5_0_ch1: ch@1 {
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compatible = "nxp,s32-psi5-channel";
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reg = <1>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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psi5_0_ch2: ch@2 {
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compatible = "nxp,s32-psi5-channel";
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reg = <2>;
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interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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psi5_0_ch3: ch@3 {
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compatible = "nxp,s32-psi5-channel";
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reg = <3>;
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interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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psi5_1: psi5@421e0000 {
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compatible = "nxp,s32-psi5";
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reg = <0x421e0000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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psi5_1_ch0: ch@0 {
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compatible = "nxp,s32-psi5-channel";
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reg = <0>;
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interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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psi5_1_ch1: ch@1 {
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compatible = "nxp,s32-psi5-channel";
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reg = <1>;
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interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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psi5_1_ch2: ch@2 {
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compatible = "nxp,s32-psi5-channel";
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reg = <2>;
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interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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psi5_1_ch3: ch@3 {
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compatible = "nxp,s32-psi5-channel";
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reg = <3>;
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interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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};
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};

west.yml

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@@ -198,7 +198,7 @@ manifest:
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groups:
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- hal
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- name: hal_nxp
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revision: 4a4741fa2be33f6b638a49e357c5e33bb7ad0544
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revision: pull/451/head
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path: modules/hal/nxp
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groups:
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- hal

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