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drivers: can: Add driver support for TI MSPM0 G-Series MCAN module
Add driver support for MCAN module on TI's MSPM0 G-Series MCUs. The MCAN module supports both classic CAN and CAN FD protocols. Signed-off-by: Santhosh Charles <[email protected]> Signed-off-by: Jackson Farley <[email protected]> Signed-off-by: Tomasz Bursztyka <[email protected]>
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‎drivers/can/CMakeLists.txt‎

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@@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_CAN_MCP2515 can_mcp2515.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_MCP251XFD can_mcp251xfd.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_MCUX_FLEXCAN can_mcux_flexcan.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_MCUX_MCAN can_mcux_mcan.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_MSPM0_CANFD can_mspm0_canfd.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_NRF can_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_NUMAKER can_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_NXP_S32_CANXL can_nxp_s32_canxl.c)

‎drivers/can/Kconfig‎

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@@ -140,6 +140,7 @@ source "drivers/can/Kconfig.nrf"
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source "drivers/can/Kconfig.renesas_ra"
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source "drivers/can/Kconfig.renesas_rz"
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source "drivers/can/Kconfig.max32"
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source "drivers/can/Kconfig.mspm0"
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source "drivers/can/transceiver/Kconfig"
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‎drivers/can/Kconfig.mspm0‎

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# Copyright (c) 2024 Texas Instruments
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# SPDX-License-Identifier: Apache-2.0
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config CAN_MSPM0_CANFD
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bool "MSPM0 CANFD driver"
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default y
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depends on DT_HAS_TI_MSPM0_CANFD_ENABLED
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select CAN_MCAN
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select USE_MSPM0_DL_MCAN
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help
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Enable support for CANFD on the TI MSPM0 series.
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if CAN_MSPM0_CANFD
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endif # CAN_MSPM0G3XXX_CANFD

‎drivers/can/can_mspm0_canfd.c‎

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/*
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* Copyright (c) 2024 Texas Instruments
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/can/can_mcan.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/mspm0_clock_control.h>
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#include <zephyr/logging/log.h>
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/* Driverlib includes */
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#include <ti/driverlib/dl_mcan.h>
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LOG_MODULE_REGISTER(can_mspm0_canfd, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT ti_mspm0_canfd
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#define CAN_MSPM0_CLK_SRC_PLLCLK1 1
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struct can_mspm0_canfd_config {
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MCAN_Regs *ti_canfd_base;
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const struct mspm0_sys_clock *clock_subsys;
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const DL_MCAN_ClockConfig clock_cfg;
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mm_reg_t mcan_base;
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mem_addr_t mram;
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void (*irq_cfg_func)(void);
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const struct pinctrl_dev_config *pinctrl;
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};
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static int can_mspm0_canfd_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_config->custom;
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return can_mcan_sys_read_reg(config->mcan_base, reg, val);
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}
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static int can_mspm0_canfd_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_config->custom;
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return can_mcan_sys_write_reg(config->mcan_base, reg, val);
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}
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static int can_mspm0_canfd_read_mram(const struct device *dev, uint16_t offset, void *dst,
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size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_config->custom;
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return can_mcan_sys_read_mram(config->mram, offset, dst, len);
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}
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static int can_mspm0_canfd_write_mram(const struct device *dev, uint16_t offset, const void *src,
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size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_config->custom;
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return can_mcan_sys_write_mram(config->mram, offset, src, len);
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}
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static int can_mspm0_canfd_clear_mram(const struct device *dev, uint16_t offset, size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_config->custom;
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return can_mcan_sys_clear_mram(config->mram, offset, len);
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}
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static int can_mspm0_canfd_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_config->custom;
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const struct device *clk_dev = DEVICE_DT_GET(DT_NODELABEL(ckm));
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uint32_t clock_rate;
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int ret;
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ret = clock_control_get_rate(clk_dev, (struct mspm0_sys_clock *)config->clock_subsys,
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&clock_rate);
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if (ret < 0) {
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return ret;
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}
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if (config->clock_cfg.divider != DL_MCAN_FCLK_DIV_1) {
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*rate = clock_rate / (config->clock_cfg.divider >> MCAN_CLKDIV_RATIO_OFS);
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} else {
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*rate = clock_rate;
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}
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return 0;
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}
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static int can_mspm0_canfd_clock_enable(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_cfg->custom;
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DL_MCAN_RevisionId revid_MCAN0;
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DL_MCAN_setClockConfig(config->ti_canfd_base,
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(DL_MCAN_ClockConfig *)&config->clock_cfg);
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/* Retrieve a valid MCANSS Revision ID after enabling the clock module.
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* The revision ID registers may initially return an invalid value until
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* the clock domain is fully stabilized.
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*/
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do {
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DL_MCAN_enableModuleClock(config->ti_canfd_base);
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DL_MCAN_getRevisionId(config->ti_canfd_base, &revid_MCAN0);
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} while ((uint32_t)revid_MCAN0.scheme == 0x00);
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return 0;
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}
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static int can_mspm0_canfd_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_cfg->custom;
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int ret = 0;
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LOG_DBG("Initializing %s", dev->name);
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ret = pinctrl_apply_state(config->pinctrl, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("MSPM0 CAN pinctrl error (%d)", ret);
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return ret;
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}
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DL_MCAN_reset(config->ti_canfd_base);
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DL_MCAN_enablePower(config->ti_canfd_base);
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delay_cycles(CONFIG_MSPM0_PERIPH_STARTUP_DELAY);
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can_mspm0_canfd_clock_enable(dev);
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while (false == DL_MCAN_isMemInitDone(config->ti_canfd_base)) {
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/* Wait for Memory initialization to be completed. */
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}
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ret = can_mcan_configure_mram(dev, 0x8000, config->mram);
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if (ret != 0) {
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return ret;
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}
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ret = can_mcan_init(dev);
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if (ret != 0) {
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return ret;
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}
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DL_MCAN_clearInterruptStatus(config->ti_canfd_base,
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(DL_MCAN_MSP_INTERRUPT_LINE0 | DL_MCAN_MSP_INTERRUPT_LINE1));
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DL_MCAN_enableInterrupt(config->ti_canfd_base,
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(DL_MCAN_MSP_INTERRUPT_LINE0 | DL_MCAN_MSP_INTERRUPT_LINE1));
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config->irq_cfg_func();
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return ret;
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}
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static void can_mspm0_canfd_isr(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_mspm0_canfd_config *config = mcan_cfg->custom;
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switch (DL_MCAN_getPendingInterrupt(config->ti_canfd_base)) {
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case DL_MCAN_IIDX_LINE0:
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can_mcan_line_0_isr(dev);
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(config->ti_canfd_base)
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->MCANSS.TI_WRAPPER.PROCESSORS.MCANSS_REGS.MCANSS_EOI =
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DL_MCAN_INTR_SRC_MCAN_LINE_0;
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break;
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case DL_MCAN_IIDX_LINE1:
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can_mcan_line_1_isr(dev);
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(config->ti_canfd_base)
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->MCANSS.TI_WRAPPER.PROCESSORS.MCANSS_REGS.MCANSS_EOI =
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DL_MCAN_INTR_SRC_MCAN_LINE_1;
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break;
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default:
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break;
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}
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}
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static const struct can_driver_api can_mspm0_canfd_driver_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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.get_state = can_mcan_get_state,
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#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
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.get_core_clock = can_mspm0_canfd_get_core_clock,
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.get_max_filters = can_mcan_get_max_filters,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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.timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
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.timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
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.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
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#endif /* CONFIG_CAN_FD_MODE */
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};
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static const struct can_mcan_ops can_mspm0_canfd_ops = {
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.read_reg = can_mspm0_canfd_read_reg,
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.write_reg = can_mspm0_canfd_write_reg,
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.read_mram = can_mspm0_canfd_read_mram,
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.write_mram = can_mspm0_canfd_write_mram,
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.clear_mram = can_mspm0_canfd_clear_mram,
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};
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#define CAN_MSPM0_CANFD_INIT(inst) \
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static void can_mspm0_canfd_irq_cfg_##inst(void) { \
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IRQ_CONNECT(DT_INST_IRQN(inst), \
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DT_INST_IRQ(inst, priority), \
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can_mspm0_canfd_isr, \
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DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQN(inst)); \
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} \
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\
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static const struct mspm0_sys_clock can_mspm0_canfd_sys_clock_##inst = \
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MSPM0_CLOCK_SUBSYS_FN(inst); \
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\
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PINCTRL_DT_INST_DEFINE(inst); \
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\
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CAN_MCAN_DT_INST_CALLBACKS_DEFINE(inst, can_mspm0_canfd_cbs_##inst); \
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\
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BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(inst) <= \
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CAN_MCAN_DT_INST_MRAM_SIZE(inst), \
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"Insufficient Message RAM size"); \
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\
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static const struct can_mspm0_canfd_config can_mspm0_canfd_cfg_##inst = { \
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.ti_canfd_base = (MCAN_Regs *)DT_REG_ADDR_BY_NAME(DT_DRV_INST(inst), ti_canfd), \
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.clock_subsys = &can_mspm0_canfd_sys_clock_##inst, \
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.clock_cfg = { \
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.clockSel = DT_PROP_OR(DT_DRV_INST(inst), ti_canclk_source, \
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CAN_MSPM0_CLK_SRC_PLLCLK1) == \
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CAN_MSPM0_CLK_SRC_PLLCLK1 \
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? DL_MCAN_FCLK_SYSPLLCLK1 \
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: DL_MCAN_FCLK_HFCLK, \
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.divider = DT_PROP(DT_DRV_INST(inst), ti_divider), \
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}, \
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.mcan_base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
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.mram = CAN_MCAN_DT_INST_MRAM_ADDR(inst), \
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.irq_cfg_func = can_mspm0_canfd_irq_cfg_##inst, \
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.pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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}; \
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\
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static struct can_mcan_data can_mcan_data_##inst = \
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CAN_MCAN_DATA_INITIALIZER(NULL); \
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\
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static const struct can_mcan_config can_mcan_cfg_##inst = \
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CAN_MCAN_DT_CONFIG_INST_GET(inst, \
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&can_mspm0_canfd_cfg_##inst, \
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&can_mspm0_canfd_ops, \
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&can_mspm0_canfd_cbs_##inst); \
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\
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CAN_DEVICE_DT_INST_DEFINE(inst, \
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can_mspm0_canfd_init, NULL, \
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&can_mcan_data_##inst, &can_mcan_cfg_##inst, \
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POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_mspm0_canfd_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(CAN_MSPM0_CANFD_INIT)

‎modules/Kconfig.mspm0‎

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@@ -14,3 +14,6 @@ config USE_MSPM0_DL_UART
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config USE_MSPM0_DL_TIMER
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bool
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config USE_MSPM0_DL_MCAN
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bool

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