boards: opta: ethernet reorganization

This set of changes reorganize the ethernet configuration by removing the
use a regulator to enable the PHY: the correct GPIO pin is set in code
only if the network has been configured via CONFIG_NET_L2_ETHERNET.

Signed-off-by: Federico Di Gregorio <[email protected]>

Author: fogzot

boards/arduino/opta/CMakeLists.txt

@@ -1,4 +1,4 @@
 #  Copyright (c) 2021 STMicroelectronics
 #  SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(board_gpio_hse.c)
+zephyr_sources(board_gpio_init.c)

boards/arduino/opta/arduino_opta-common.dtsi

@@ -87,3 +87,7 @@
 &mailbox {
 	status = "okay";
 };
+
+&rng {
+	status = "okay";
+};

boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts

@@ -24,14 +24,6 @@
 		zephyr,code-partition = &slot0_partition;
 	};
 
-	ethernet_phy_en: ethernet_phy_en {
-		compatible = "regulator-fixed";
-		regulator-name = "ethernet-phy-reset-release";
-		enable-gpios = <&gpioj 15 GPIO_ACTIVE_HIGH>;
-		regulator-boot-on;
-		status = "okay";
-	};
-
 	sdram2: sdram@d0000000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		device_type = "memory";
@@ -101,6 +93,7 @@ zephyr_udc0: &usbotg_fs {
 	};
 };
 
+/* Assign USB to M7 by default */
 &usbotg_fs {
 	status = "okay";
 };
@@ -109,10 +102,7 @@ zephyr_udc0: &usbotg_fs {
 	status = "disabled";
 };
 
-&cdc_acm_uart0 {
-	status = "okay";
-};
-
+/* Assign ethernet to M7 by default */
 &mac {
 	pinctrl-0 = <
 		&eth_ref_clk_pa1
@@ -128,9 +118,9 @@ zephyr_udc0: &usbotg_fs {
 };
 
 &mdio {
-	status = "okay";
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
+	status = "okay";
 
 	ethernet-phy@0 {
 		compatible = "ethernet-phy";
@@ -139,6 +129,7 @@ zephyr_udc0: &usbotg_fs {
 	};
 };
 
-&rng {
+/* Assign USB serial (ACM) to M7 to have a working console out of the box */
+&cdc_acm_uart0 {
 	status = "okay";
 };

boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig

@@ -31,7 +31,3 @@ CONFIG_UART_LINE_CTRL=y
 
 # Enable USB Stack (needed for the console to work)
 CONFIG_USB_DEVICE_STACK=y
-
-# Enable regulator (needed to enable eth)
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED=y

boards/arduino/opta/board_gpio_hse.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2024 DNDG srl
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/init.h>
+#include <stm32h7xx_ll_bus.h>
+#include <stm32h7xx_ll_gpio.h>
+
+static int board_gpio_init(void)
+{
+	/* The external oscillator that drives the HSE clock should be enabled
+	 * by setting the GPIOI1 pin. This function is registered at priority
+	 * RE_KERNEL_1 to be executed before the standard STM clock
+	 * setup code.
+	 *
+	 * Note that the HSE should be turned on by the M7 only because M4
+	 * is not booted by default on Opta and cannot configure the clocks
+	 * anyway.
+	 */
+#ifdef CONFIG_BOARD_ARDUINO_OPTA_STM32H747XX_M7
+	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH);
+	LL_GPIO_SetPinMode(GPIOH, LL_GPIO_PIN_1, LL_GPIO_MODE_OUTPUT);
+	LL_GPIO_SetPinSpeed(GPIOH, LL_GPIO_PIN_1, LL_GPIO_SPEED_FREQ_LOW);
+	LL_GPIO_SetPinOutputType(GPIOH, LL_GPIO_PIN_1, LL_GPIO_OUTPUT_PUSHPULL);
+	LL_GPIO_SetPinPull(GPIOH, LL_GPIO_PIN_1, LL_GPIO_PULL_UP);
+	LL_GPIO_SetOutputPin(GPIOH, LL_GPIO_PIN_1);
+#endif
+
+	/* The ethernet adapter is enabled by settig the GPIOJ15 pin to 1.
+	 * This is done only if the network has been explicitly configured
+	 */
+#ifdef CONFIG_NET_L2_ETHERNET
+	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOJ);
+	LL_GPIO_SetPinMode(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_MODE_OUTPUT);
+	LL_GPIO_SetPinSpeed(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_SPEED_FREQ_LOW);
+	LL_GPIO_SetPinOutputType(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_OUTPUT_PUSHPULL);
+	LL_GPIO_SetPinPull(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_PULL_UP);
+	LL_GPIO_SetOutputPin(GPIOJ, LL_GPIO_PIN_15);
+#endif
+
+	return 0;
+}
+
+SYS_INIT(board_gpio_init, PRE_KERNEL_1, 0);

boards/arduino/opta/board_gpio_init.c

@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2024 DNDG srl
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mac {
+	status = "okay";
+};