dts: stm32: stm32h7rs: Add sdmmc1 and sdmmc2 configuration

Provide the soc configuration for sdmmc1 and sdmmc2 controllers.
This includes registers address, clocks, resets and interrupt line
details.

Signed-off-by: Shan Pen <[email protected]>

Author: bricle

dts/arm/st/h7rs/stm32h7rs.dtsi

@@ -908,6 +908,26 @@
 			resets = <&rctl STM32_RESET(APB5, 1)>;
 			status = "disabled";
 		};
+
+		sdmmc1: sdmmc@52007000 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x52007000 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB5, 8)>,
+				 <&rcc STM32_SRC_PLL2_S SDMMC_SEL(0)>;
+			resets = <&rctl STM32_RESET(AHB5, 8)>;
+			interrupts = <108 0>;
+			status = "disabled";
+		};
+
+		sdmmc2: sdmmc@48002400 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x48002400 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 9)>,
+				 <&rcc STM32_SRC_PLL2_S SDMMC_SEL(0)>;
+			resets = <&rctl STM32_RESET(AHB2, 9)>;
+			interrupts = <109 0>;
+			status = "disabled";
+		};
 	};
 
 	otgfs_phy: otgfs_phy {