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Jakub Wasilewskinashif
Jakub Wasilewski
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nashif
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drivers: eeprom: add mb85rsm1t fram support
Add a driver for the MB85RSM1T FRAM chip. Signed-off-by: Jakub Wasilewski <[email protected]> Signed-off-by: Filip Kokosinski <[email protected]>
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‎drivers/eeprom/CMakeLists.txt‎

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@@ -26,3 +26,5 @@ zephyr_library_sources_ifdef(CONFIG_EEPROM_FAKE eeprom_fake.c)
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zephyr_library_sources_ifdef(CONFIG_EEPROM_AT2X_EMUL eeprom_at2x_emul.c)
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zephyr_library_sources_ifdef(CONFIG_EEPROM_MB85RCXX eeprom_mb85rcxx.c)
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zephyr_library_sources_ifdef(CONFIG_EEPROM_MB85RSXX eeprom_mb85rsxx.c)

‎drivers/eeprom/Kconfig‎

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@@ -99,6 +99,7 @@ source "drivers/eeprom/Kconfig.eeprom_emu"
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source "drivers/eeprom/Kconfig.tmp116"
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source "drivers/eeprom/Kconfig.xec"
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source "drivers/eeprom/Kconfig.mb85rcxx"
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source "drivers/eeprom/Kconfig.mb85rsxx"
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config EEPROM_SIMULATOR
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bool "Simulated EEPROM driver"

‎drivers/eeprom/Kconfig.mb85rsxx‎

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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config EEPROM_MB85RSXX
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bool "FUJITSU MB85RSXX SPI FRAM"
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default y
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depends on DT_HAS_FUJITSU_MB85RSXX_ENABLED
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select SPI
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help
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Enable FUJITSU mb85rsxx SPI FRAM

‎drivers/eeprom/eeprom_mb85rsxx.c‎

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/*
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* Copyright (c) 2024 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Driver for Fujitsu MB85RSXX FRAM over SPI.
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*/
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#define DT_DRV_COMPAT fujitsu_mb85rsxx
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#include <zephyr/device.h>
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#include <zephyr/drivers/eeprom.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(mb85rsxx, CONFIG_EEPROM_LOG_LEVEL);
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/* MB85RSXX instruction set */
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#define EEPROM_MB85RSXX_WREN 0x06U /* Set Write Enable Latch */
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#define EEPROM_MB85RSXX_WRDI 0x04U /* Reset Write Enable Latch */
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#define EEPROM_MB85RSXX_RDSR 0x05U /* Read Status Register */
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#define EEPROM_MB85RSXX_WRSR 0x01U /* Write Status Register */
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#define EEPROM_MB85RSXX_READ 0x03U /* Read Memory Code */
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#define EEPROM_MB85RSXX_WRITE 0x02U /* Write Memory Code */
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#define EEPROM_MB85RSXX_RDID 0x9FU /* Read Device ID */
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#define EEPROM_MB85RSXX_FSTRD 0x0BU /* Fast Read Memory Code */
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#define EEPROM_MB85RSXX_SLEEP 0xB9U /* Sleep Mode */
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/* MB85RSXX status register bits */
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#define EEPROM_MB85RSXX_STATUS_WPEN BIT(7) /* Status Register Write Protect (RW) */
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#define EEPROM_MB85RSXX_STATUS_BP1 BIT(3) /* Block protection 1 (RW) */
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#define EEPROM_MB85RSXX_STATUS_BP0 BIT(2) /* Block protection 2 (RW) */
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#define EEPROM_MB85RSXX_STATUS_WEL BIT(1) /* Write Enable Latch (RO) */
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/* Fujitsu manufacturer ID (2 bytes) */
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#define EEPROM_MB85RSXX_MAN_ID 0x04U
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#define EEPROM_MB85RSXX_CON_CODE 0x7FU
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/*
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* MB85RSXX product ID (2 bytes); first byte provides memory size, so let's use a mask later when
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* checking it
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*/
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#define EEPROM_MB85RSXX_PROD_ID 0x20U
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#define EEPROM_MB85RSXX_PROD_ID2 0x03U
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#define EEPROM_MB85RSXX_PROD_MASK GENMASK(7, 5)
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struct eeprom_mb85rsxx_config {
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struct spi_dt_spec spi;
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size_t size;
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bool readonly;
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};
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struct eeprom_mb85rsxx_data {
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struct k_mutex lock;
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};
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static int eeprom_mb85rsxx_read(const struct device *dev, off_t offset, void *buf, size_t len)
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{
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const struct eeprom_mb85rsxx_config *config = dev->config;
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struct eeprom_mb85rsxx_data *data = dev->data;
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uint8_t cmd[4] = {EEPROM_MB85RSXX_READ, 0, 0, 0};
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uint8_t *paddr = &cmd[1];
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int err;
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if (offset + len > config->size) {
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LOG_ERR("attempt to read past device boundary");
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return -EINVAL;
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}
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if (!len) {
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return 0;
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}
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/* Populate address in command */
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*paddr++ = (offset >> 16);
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*paddr++ = (offset >> 8);
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*paddr++ = offset;
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const struct spi_buf tx_buf = {
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.buf = cmd,
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.len = sizeof(cmd),
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_bufs[2] = {
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{
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.buf = NULL,
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.len = sizeof(cmd),
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},
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{
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.buf = buf,
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.len = len,
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},
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};
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const struct spi_buf_set rx = {
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.buffers = rx_bufs,
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.count = ARRAY_SIZE(rx_bufs),
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};
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k_mutex_lock(&data->lock, K_FOREVER);
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err = spi_transceive_dt(&config->spi, &tx, &rx);
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k_mutex_unlock(&data->lock);
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if (err < 0) {
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LOG_ERR("failed to read FRAM (err %d)", err);
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}
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return err;
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}
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static int eeprom_mb85rsxx_wren(const struct device *dev)
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{
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const struct eeprom_mb85rsxx_config *config = dev->config;
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uint8_t cmd = EEPROM_MB85RSXX_WREN;
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const struct spi_buf tx_buf = {
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.buf = &cmd,
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.len = sizeof(cmd),
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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return spi_write_dt(&config->spi, &tx);
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}
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static int eeprom_mb85rsxx_wrdi(const struct device *dev)
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{
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const struct eeprom_mb85rsxx_config *config = dev->config;
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uint8_t cmd = EEPROM_MB85RSXX_WRDI;
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const struct spi_buf tx_buf = {
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.buf = &cmd,
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.len = sizeof(cmd),
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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return spi_write_dt(&config->spi, &tx);
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}
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static int eeprom_mb85rsxx_write(const struct device *dev, off_t offset, const void *buf,
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size_t len)
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{
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const struct eeprom_mb85rsxx_config *config = dev->config;
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struct eeprom_mb85rsxx_data *data = dev->data;
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uint8_t cmd[4] = {EEPROM_MB85RSXX_WRITE, 0, 0, 0};
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uint8_t *paddr = &cmd[1];
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int err;
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if (config->readonly) {
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LOG_ERR("attempt to write to read-only device");
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return -EACCES;
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}
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if (offset + len > config->size) {
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LOG_ERR("attempt to write past device boundary");
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return -EINVAL;
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}
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/* Populate address in command */
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*paddr++ = (offset >> 16) & 0xFF;
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*paddr++ = (offset >> 8) & 0xFF;
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*paddr++ = offset & 0xFF;
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const struct spi_buf tx_bufs[2] = {
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{
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.buf = cmd,
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.len = sizeof(cmd),
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},
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{
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.buf = (void *)buf,
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.len = len,
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},
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};
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const struct spi_buf_set tx = {
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.buffers = tx_bufs,
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.count = ARRAY_SIZE(tx_bufs),
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};
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k_mutex_lock(&data->lock, K_FOREVER);
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err = eeprom_mb85rsxx_wren(dev);
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if (err < 0) {
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LOG_ERR("failed to disable write protection (err %d)", err);
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k_mutex_unlock(&data->lock);
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return err;
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}
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err = spi_write_dt(&config->spi, &tx);
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if (err < 0) {
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LOG_ERR("failed to write to FRAM (err %d)", err);
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k_mutex_unlock(&data->lock);
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return err;
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}
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err = eeprom_mb85rsxx_wrdi(dev);
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if (err < 0) {
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LOG_ERR("failed to disable write (err %d)", err);
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}
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k_mutex_unlock(&data->lock);
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return err;
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}
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static size_t eeprom_mb85rsxx_size(const struct device *dev)
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{
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const struct eeprom_mb85rsxx_config *config = dev->config;
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return config->size;
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}
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static int eeprom_mb85rsxx_rdid(const struct device *dev)
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{
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const struct eeprom_mb85rsxx_config *config = dev->config;
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struct eeprom_mb85rsxx_data *data = dev->data;
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uint8_t id[4];
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uint8_t cmd = EEPROM_MB85RSXX_RDID;
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int err;
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const struct spi_buf tx_buf = {
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.buf = &cmd,
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.len = sizeof(cmd),
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_bufs[2] = {
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{
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.buf = NULL,
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.len = sizeof(cmd),
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},
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{
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.buf = id,
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.len = sizeof(id),
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},
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};
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const struct spi_buf_set rx = {
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.buffers = rx_bufs,
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.count = ARRAY_SIZE(rx_bufs),
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};
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k_mutex_lock(&data->lock, K_FOREVER);
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err = spi_transceive_dt(&config->spi, &tx, &rx);
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k_mutex_unlock(&data->lock);
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if (err < 0) {
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LOG_ERR("failed to read RDID (err %d)", err);
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return err;
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}
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/* Validate Manufacturer ID and Product ID */
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if (id[0] != EEPROM_MB85RSXX_MAN_ID
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|| id[1] != EEPROM_MB85RSXX_CON_CODE
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|| (id[2] & EEPROM_MB85RSXX_PROD_MASK) != EEPROM_MB85RSXX_PROD_ID
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|| id[3] != EEPROM_MB85RSXX_PROD_ID2) {
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LOG_ERR("invalid device ID: %02X %02X %02X %02X", id[0], id[1], id[2], id[3]);
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return -EIO;
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}
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LOG_INF("device ID read successfully: %02X %02X %02X %02X", id[0], id[1], id[2], id[3]);
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return 0;
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}
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static int eeprom_mb85rsxx_init(const struct device *dev)
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{
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const struct eeprom_mb85rsxx_config *config = dev->config;
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struct eeprom_mb85rsxx_data *data = dev->data;
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int err;
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k_mutex_init(&data->lock);
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if (!spi_is_ready_dt(&config->spi)) {
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LOG_ERR("SPI bus not ready");
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return -EINVAL;
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}
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err = eeprom_mb85rsxx_rdid(dev);
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if (err < 0) {
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LOG_ERR("Failed to initialize device, RDID check failed (err %d)", err);
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return err;
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}
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return 0;
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}
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static const struct eeprom_driver_api mb85rsxx_driver_api = {
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.read = &eeprom_mb85rsxx_read,
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.write = &eeprom_mb85rsxx_write,
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.size = &eeprom_mb85rsxx_size,
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};
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#define MB85RSXX_INIT(inst) \
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static struct eeprom_mb85rsxx_data eeprom_mb85rsxx_data_##inst; \
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\
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static const struct eeprom_mb85rsxx_config eeprom_mb85rsxx_config_##inst = { \
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.spi = SPI_DT_SPEC_INST_GET( \
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inst, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0), \
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.size = DT_INST_PROP(inst, size), \
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.readonly = DT_INST_PROP(inst, read_only), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, eeprom_mb85rsxx_init, NULL, &eeprom_mb85rsxx_data_##inst, \
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&eeprom_mb85rsxx_config_##inst, POST_KERNEL, \
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CONFIG_EEPROM_INIT_PRIORITY, &mb85rsxx_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(MB85RSXX_INIT)

‎dts/bindings/mtd/fujitsu,mb85rsxx.yaml‎

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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Fujitsu MB85RSXX SPI FRAM
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compatible: "fujitsu,mb85rsxx"
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include: ["eeprom-base.yaml", spi-device.yaml]
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properties:
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size:
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required: true
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description: Total FRAM size in bytes.

‎tests/drivers/build_all/eeprom/app.overlay‎

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* (and be extended to test) real hardware.
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*/
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#include <freq.h>
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#include <mem.h>
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/ {
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test {
1518
#address-cells = <1>;
@@ -89,6 +92,13 @@
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wp-gpios = <&test_gpio 0 0>;
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/* read-only; */
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};
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test_spi_mb85rsxx: mb85rsxx@0 {
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compatible = "fujitsu,mb85rsxx";
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reg = <0x0>;
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spi-max-frequency = <DT_FREQ_M(25)>;
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size = <DT_SIZE_K(128)>;
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};
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};
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};
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};

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