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112 | 112 | zephyr,memory-region = "SRAM2"; |
113 | 113 | }; |
114 | 114 |
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| 115 | + dcache0: dcache0@3f400000 { |
| 116 | + compatible = "zephyr,memory-region", "mmio-sram"; |
| 117 | + reg = <0x3f400000 DT_SIZE_M(4)>; |
| 118 | + zephyr,memory-region = "DCACHE0"; |
| 119 | + }; |
| 120 | + |
| 121 | + dcache1: dcache1@3f800000 { |
| 122 | + compatible = "zephyr,memory-region", "mmio-sram"; |
| 123 | + reg = <0x3f800000 DT_SIZE_M(4)>; |
| 124 | + zephyr,memory-region = "DCACHE1"; |
| 125 | + |
| 126 | + psram0: psram0 { |
| 127 | + compatible = "espressif,esp32-psram"; |
| 128 | + size = <0x0>; |
| 129 | + }; |
| 130 | + }; |
| 131 | + |
| 132 | + icache0: icache0@400d0000 { |
| 133 | + compatible = "zephyr,memory-region", "mmio-sram"; |
| 134 | + reg = <0x400d0000 DT_SIZE_K(11456)>; |
| 135 | + zephyr,memory-region = "ICACHE0"; |
| 136 | + }; |
| 137 | + |
115 | 138 | ipmmem0: memory@3ffe5230 { |
116 | 139 | compatible = "mmio-sram"; |
117 | 140 | reg = <0x3ffe5230 0x400>; |
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189 | 212 | }; |
190 | 213 | }; |
191 | 214 |
|
192 | | - psram0: psram@3f800000 { |
193 | | - device_type = "memory"; |
194 | | - compatible = "mmio-sram"; |
195 | | - /* PSRAM size is specified in SOC/SIP dtsi */ |
196 | | - reg = <0x3f800000 DT_SIZE_M(2)>; |
197 | | - status = "disabled"; |
198 | | - }; |
199 | | - |
200 | 215 | ipi0: ipi@3f4c0058 { |
201 | 216 | compatible = "espressif,crosscore-interrupt"; |
202 | 217 | reg = <0x3f4c0058 0x4>; |
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