drivers: memc: stm32_ospi_psram: make NCS boundary configurable in dt

Limit a transaction to a boundary of aligned addresses. Each PSRAM may
specify different configuration.

Signed-off-by: Arthur Gay <[email protected]>

Author: arthur-mmlw

drivers/memc/memc_stm32_ospi_psram.c

@@ -435,7 +435,7 @@ static struct memc_stm32_ospi_psram_data memc_stm32_ospi_data = {
 			.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED,
 			.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE,
 			.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE,
-			.ChipSelectBoundary = 10,
+			.ChipSelectBoundary = DT_INST_PROP(0, st_csbound),
 			.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED,
 			.MaxTran = 0,
 			.Refresh = 320,

dts/bindings/memory-controllers/st,stm32-ospi-psram.yaml

@@ -147,3 +147,16 @@ properties:
       If enabled, the device will burst through the initial wrapped burst length
       once, then continue to burst incrementally up to maximum column address
       (1K) before wrapping around within the entire column address space.
+
+  st,csbound:
+    type: int
+    default: 3
+    description: |
+      Limit a transaction to a boundary of aligned addresses. The size of the
+      alignment is given by the value: 2^(csbound) bits.
+      A csbound value of 0 means the feature is disabled.
+      The default is the minimum recommended value in the Reference Manual. It
+      is recommended to set this value according to the length of the burst wrap
+      of the PSRAM device for the linear burst command.
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+           21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]