Skip to content

Commit d235a88

Browse files
aailletaaillet
committed
drivers: clock: rcar: Add r8a779f0 support
r8a779f0 has its own clock tree. Gen4 SoCs common registers addresses have been added. Signed-off-by: Aymeric Aillet <[email protected]> Signed-off-by: Pierre Marzin <[email protected]>
1 parent 26408e3 commit d235a88

File tree

6 files changed

+212
-3
lines changed

6 files changed

+212
-3
lines changed

‎drivers/clock_control/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_AGILEX clock_agilex.c)
5757
if(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR)
5858
zephyr_library_sources(clock_control_renesas_cpg_mssr.c)
5959
zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951 clock_control_r8a7795_cpg_mssr.c)
60+
zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 clock_control_r8a779f0_cpg_mssr.c)
6061
endif()
6162

6263
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c)

‎drivers/clock_control/Kconfig.rcar‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
# Copyright (c) 2021-2022 IoT.bzh
1+
# Copyright (c) 2021-2023 IoT.bzh
22
# SPDX-License-Identifier: Apache-2.0
33

44
config CLOCK_CONTROL_RCAR_CPG_MSSR
55
bool "RCar CPG MSSR driver"
66
default y
7-
depends on DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED
7+
depends on SOC_FAMILY_RCAR
88
help
99
Enable support for Renesas RCar CPG MSSR driver.

‎drivers/clock_control/clock_control_r8a779f0_cpg_mssr.c‎

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
1+
/*
2+
* Copyright (c) 2023 IoT.bzh
3+
*
4+
* r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
5+
*
6+
* SPDX-License-Identifier: Apache-2.0
7+
*/
8+
9+
#define DT_DRV_COMPAT renesas_r8a779f0_cpg_mssr
10+
11+
#include <errno.h>
12+
#include <soc.h>
13+
#include <zephyr/drivers/clock_control.h>
14+
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
15+
#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
16+
#include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
17+
#include <zephyr/irq.h>
18+
#include "clock_control_renesas_cpg_mssr.h"
19+
20+
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
21+
#include <zephyr/logging/log.h>
22+
LOG_MODULE_REGISTER(clock_control_rcar);
23+
24+
struct r8a779f0_cpg_mssr_config {
25+
mm_reg_t base_address;
26+
};
27+
28+
int r8a779f0_cpg_mssr_start_stop(const struct device *dev,
29+
clock_control_subsys_t sys, bool enable)
30+
{
31+
const struct r8a779f0_cpg_mssr_config *config = dev->config;
32+
struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys;
33+
int ret = -EINVAL;
34+
35+
if (clk->domain == CPG_MOD) {
36+
ret = rcar_cpg_mstp_clock_endisable(config->base_address, clk->module, enable);
37+
}
38+
39+
return ret;
40+
}
41+
42+
static int r8a779f0_cpg_mssr_start(const struct device *dev,
43+
clock_control_subsys_t sys)
44+
{
45+
return r8a779f0_cpg_mssr_start_stop(dev, sys, true);
46+
}
47+
48+
static int r8a779f0_cpg_mssr_stop(const struct device *dev,
49+
clock_control_subsys_t sys)
50+
{
51+
return r8a779f0_cpg_mssr_start_stop(dev, sys, false);
52+
}
53+
54+
static int r8a779f0_cpg_get_rate(const struct device *dev,
55+
clock_control_subsys_t sys,
56+
uint32_t *rate)
57+
{
58+
struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys;
59+
int ret = 0;
60+
61+
if (clk->domain != CPG_CORE) {
62+
return -ENOTSUP;
63+
}
64+
65+
switch (clk->module) {
66+
case R8A779F0_CLK_S0D12_PER:
67+
*rate = S0D12_PER_CLK_RATE;
68+
break;
69+
default:
70+
ret = -ENOTSUP;
71+
break;
72+
}
73+
74+
return ret;
75+
}
76+
77+
static int r8a779f0_cpg_mssr_init(const struct device *dev)
78+
{
79+
ARG_UNUSED(dev);
80+
return 0;
81+
}
82+
83+
static const struct clock_control_driver_api r8a779f0_cpg_mssr_api = {
84+
.on = r8a779f0_cpg_mssr_start,
85+
.off = r8a779f0_cpg_mssr_stop,
86+
.get_rate = r8a779f0_cpg_get_rate,
87+
};
88+
89+
#define R8A779f0_MSSR_INIT(inst) \
90+
static struct r8a779f0_cpg_mssr_config r8a779f0_cpg_mssr##inst##_config = { \
91+
.base_address = DT_INST_REG_ADDR(inst) \
92+
}; \
93+
\
94+
DEVICE_DT_INST_DEFINE(inst, \
95+
&r8a779f0_cpg_mssr_init, \
96+
NULL, \
97+
NULL, &r8a779f0_cpg_mssr##inst##_config, \
98+
PRE_KERNEL_1, \
99+
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
100+
&r8a779f0_cpg_mssr_api);
101+
102+
DT_INST_FOREACH_STATUS_OKAY(R8A779f0_MSSR_INIT)

‎drivers/clock_control/clock_control_renesas_cpg_mssr.h‎

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2022 IoT.bzh
2+
* Copyright (c) 2022-2023 IoT.bzh
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -41,6 +41,37 @@ static const uint16_t srcr[] = {
4141
/* Peripherals Clocks */
4242
#define S3D4_CLK_RATE 66600000 /* SCIF */
4343
#define S0D12_CLK_RATE 66600000 /* PWM */
44+
#elif CONFIG_SOC_SERIES_RCAR_GEN4
45+
/* Software Reset Clearing Register offsets */
46+
#define SRSTCLR(i) (0x2C80 + (i) * 4)
47+
48+
/* CPG write protect offset */
49+
#define CPGWPR 0x000
50+
51+
/* Module Stop Control Register offsets */
52+
static const uint16_t mstpcr[] = {
53+
0x2D00, 0x2D04, 0x2D08, 0x2D0C,
54+
0x2D10, 0x2D14, 0x2D18, 0x2D1C,
55+
0x2D20, 0x2D24, 0x2D28, 0x2D2C,
56+
0x2D30, 0x2D34, 0x2D38, 0x2D3C,
57+
0x2D40, 0x2D44, 0x2D48, 0x2D4C,
58+
0x2D50, 0x2D54, 0x2D58, 0x2D5C,
59+
0x2D60, 0x2D64, 0x2D68, 0x2D6C,
60+
};
61+
62+
/* Software Reset Register offsets */
63+
static const uint16_t srcr[] = {
64+
0x2C00, 0x2C04, 0x2C08, 0x2C0C,
65+
0x2C10, 0x2C14, 0x2C18, 0x2C1C,
66+
0x2C20, 0x2C24, 0x2C28, 0x2C2C,
67+
0x2C30, 0x2C34, 0x2C38, 0x2C3C,
68+
0x2C40, 0x2C44, 0x2C48, 0x2C4C,
69+
0x2C50, 0x2C54, 0x2C58, 0x2C5C,
70+
0x2C60, 0x2C64, 0x2C68, 0x2C6C,
71+
};
72+
73+
/* Peripherals Clocks */
74+
#define S0D12_PER_CLK_RATE 66600000 /* SCIF */
4475
#endif /* CONFIG_SOC_SERIES_RCAR_GEN3 */
4576

4677
void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val);

‎dts/bindings/clock/renesas,r8a779f0-cpg-mssr.yaml‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
# Copyright (c) 2023 IoT.bzh
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
description: Renesas R8A779F0 SoC Clock Pulse Generator / Module Standby and Software Reset
5+
6+
compatible: "renesas,r8a779f0-cpg-mssr"
7+
8+
include: renesas,rcar-cpg-mssr.yaml

‎include/zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
/*
2+
* Copyright (c) 2023 IoT.bzh
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_
8+
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_
9+
10+
#include "renesas_cpg_mssr.h"
11+
12+
/* r8a779f0 CPG Core Clocks */
13+
#define R8A779F0_CLK_Z0 0
14+
#define R8A779F0_CLK_Z1 1
15+
#define R8A779F0_CLK_ZR 2
16+
#define R8A779F0_CLK_ZX 3
17+
#define R8A779F0_CLK_ZS 4
18+
#define R8A779F0_CLK_ZT 5
19+
#define R8A779F0_CLK_ZTR 6
20+
#define R8A779F0_CLK_S0D2 7
21+
#define R8A779F0_CLK_S0D3 8
22+
#define R8A779F0_CLK_S0D4 9
23+
#define R8A779F0_CLK_S0D2_MM 10
24+
#define R8A779F0_CLK_S0D3_MM 11
25+
#define R8A779F0_CLK_S0D4_MM 12
26+
#define R8A779F0_CLK_S0D2_RT 13
27+
#define R8A779F0_CLK_S0D3_RT 14
28+
#define R8A779F0_CLK_S0D4_RT 15
29+
#define R8A779F0_CLK_S0D6_RT 16
30+
#define R8A779F0_CLK_S0D3_PER 17
31+
#define R8A779F0_CLK_S0D6_PER 18
32+
#define R8A779F0_CLK_S0D12_PER 19 /* SCIF Clock */
33+
#define R8A779F0_CLK_S0D24_PER 20
34+
#define R8A779F0_CLK_S0D2_HSC 21
35+
#define R8A779F0_CLK_S0D3_HSC 22
36+
#define R8A779F0_CLK_S0D4_HSC 23
37+
#define R8A779F0_CLK_S0D6_HSC 24
38+
#define R8A779F0_CLK_S0D12_HSC 25
39+
#define R8A779F0_CLK_S0D2_CC 26
40+
#define R8A779F0_CLK_CL 27
41+
#define R8A779F0_CLK_CL16M 28
42+
#define R8A779F0_CLK_CL16M_MM 29
43+
#define R8A779F0_CLK_CL16M_RT 30
44+
#define R8A779F0_CLK_CL16M_PER 31
45+
#define R8A779F0_CLK_CL16M_HSC 32
46+
#define R8A779F0_CLK_ZB3 33
47+
#define R8A779F0_CLK_ZB3D2 34
48+
#define R8A779F0_CLK_ZB3D4 35
49+
#define R8A779F0_CLK_SD0H 36
50+
#define R8A779F0_CLK_SD0 37
51+
#define R8A779F0_CLK_RPC 38
52+
#define R8A779F0_CLK_RPCD2 39
53+
#define R8A779F0_CLK_MSO 40
54+
#define R8A779F0_CLK_POST 41
55+
#define R8A779F0_CLK_POST2 42
56+
#define R8A779F0_CLK_SASYNCRT 43
57+
#define R8A779F0_CLK_SASYNCPERD1 44
58+
#define R8A779F0_CLK_SASYNCPERD2 45
59+
#define R8A779F0_CLK_SASYNCPERD4 46
60+
#define R8A779F0_CLK_DBGSOC_HSC 47
61+
#define R8A779F0_CLK_RSW2 48
62+
#define R8A779F0_CLK_CPEX 49
63+
#define R8A779F0_CLK_CBFUSA 50
64+
#define R8A779F0_CLK_R 51
65+
#define R8A779F0_CLK_OSC 52
66+
67+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ */

0 commit comments

Comments
 (0)