Skip to content

Commit d33d5b3

Browse files
ozersajpmur
authored and
henrikbrixandersen
committed
soc: Add the MAX32690 SoC
Added ADI MAX series soc, first partnumber is MAX32690 The family structure will be ADI_MAX MAX32xxx MAX32655 MAX32655EVKIT MAX32655FTHR MAX32666 MAX32666FTHR MAX32666FTHR2 MAX32690 MAX32690EVKIT MAX78xxx MAX78000 MAX78002 ... When MAX32 MCUs goes to sleep mode debugger could not access it and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent the CPU from actually entering sleep by skipping the WFE/WFI instruction. Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK. If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y) devicei will not goes to sleep mode in idle state. To disable it add below line in your configuration file CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core support. Co-authored-by: Jason Murphy <[email protected]> Signed-off-by: Sadik Ozer <[email protected]>
1 parent 0480b26 commit d33d5b3

File tree

11 files changed

+1208
-0
lines changed

11 files changed

+1208
-0
lines changed

‎dts/arm/adi/max32/max32690-pinctrl.dtsi‎

Lines changed: 771 additions & 0 deletions
Large diffs are not rendered by default.

‎dts/arm/adi/max32/max32690.dtsi‎

Lines changed: 123 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,123 @@
1+
/*
2+
* Copyright (c) 2023-2024 Analog Devices, Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <arm/armv7-m.dtsi>
8+
#include <adi/max32/max32xxx.dtsi>
9+
10+
&clk_ipo {
11+
clock-frequency = <DT_FREQ_M(120)>;
12+
};
13+
14+
&sram0 {
15+
reg = <0x20000000 DT_SIZE_K(128)>;
16+
};
17+
18+
&flash0 {
19+
reg = <0x10000000 DT_SIZE_M(3)>;
20+
erase-block-size = <16384>;
21+
};
22+
23+
&gcr {
24+
/delete-property/ sysclk-prescaler;
25+
};
26+
27+
&pinctrl {
28+
reg = <0x40008000 0x3220>;
29+
30+
gpio2: gpio@4000a000 {
31+
reg = <0x4000a000 0x1000>;
32+
compatible = "adi,max32-gpio";
33+
gpio-controller;
34+
#gpio-cells = <2>;
35+
interrupts = <26 0>;
36+
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 2>;
37+
status = "disabled";
38+
};
39+
40+
gpio3: gpio@40080400 {
41+
reg = <0x40080400 0x200>;
42+
compatible = "adi,max32-gpio";
43+
gpio-controller;
44+
#gpio-cells = <2>;
45+
interrupts = <58 0>;
46+
clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
47+
status = "disabled";
48+
};
49+
50+
gpio4: gpio@4000c000 {
51+
reg = <0x4000c000 0x20>;
52+
compatible = "adi,max32-gpio";
53+
gpio-controller;
54+
#gpio-cells = <2>;
55+
interrupts = <54 0>;
56+
status = "disabled";
57+
};
58+
};
59+
60+
/* MAX32690 extra peripherals. */
61+
/ {
62+
soc {
63+
sram1: memory@20020000 {
64+
compatible = "mmio-sram";
65+
reg = <0x20020000 DT_SIZE_K(128)>;
66+
};
67+
68+
sram2: memory@20040000 {
69+
compatible = "mmio-sram";
70+
reg = <0x20040000 DT_SIZE_K(128)>;
71+
};
72+
73+
sram3: memory@20060000 {
74+
compatible = "mmio-sram";
75+
reg = <0x20060000 DT_SIZE_K(128)>;
76+
};
77+
78+
sram4: memory@20080000 {
79+
compatible = "mmio-sram";
80+
reg = <0x20080000 DT_SIZE_K(128)>;
81+
};
82+
83+
sram5: memory@200a0000 {
84+
compatible = "mmio-sram";
85+
reg = <0x200a0000 DT_SIZE_K(128)>;
86+
};
87+
88+
sram6: memory@200c0000 {
89+
compatible = "mmio-sram";
90+
reg = <0x200c0000 DT_SIZE_K(64)>;
91+
};
92+
93+
sram7: memory@200d0000 {
94+
compatible = "mmio-sram";
95+
reg = <0x200d0000 DT_SIZE_K(64)>;
96+
};
97+
98+
flc1: flash_controller@40029400 {
99+
compatible = "adi,max32-flash-controller";
100+
reg = <0x40029400 0x400>;
101+
102+
#address-cells = <1>;
103+
#size-cells = <1>;
104+
status = "okay";
105+
106+
flash1: flash@10080000 {
107+
compatible = "soc-nv-flash";
108+
reg = <0x10080000 DT_SIZE_K(256)>;
109+
write-block-size = <16>;
110+
erase-block-size = <16384>;
111+
};
112+
};
113+
114+
uart3: serial@40081400 {
115+
compatible = "adi,max32-uart";
116+
reg = <0x40081400 0x400>;
117+
clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
118+
clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
119+
interrupts = <88 0>;
120+
status = "disabled";
121+
};
122+
};
123+
};

‎dts/arm/adi/max32/max32xxx.dtsi‎

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,162 @@
1+
/*
2+
* Copyright (c) 2023-2024 Analog Devices, Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <mem.h>
8+
#include <zephyr/dt-bindings/gpio/gpio.h>
9+
#include <zephyr/dt-bindings/clock/adi_max32_clock.h>
10+
11+
#include <freq.h>
12+
13+
/ {
14+
chosen {
15+
zephyr,flash-controller = &flc0;
16+
};
17+
18+
cpus {
19+
#address-cells = <1>;
20+
#size-cells = <0>;
21+
22+
cpu0: cpu@0 {
23+
device_type = "cpu";
24+
compatible = "arm,cortex-m4f";
25+
reg = <0>;
26+
};
27+
};
28+
29+
clocks {
30+
clk_ipo: clk_ipo {
31+
compatible = "fixed-clock";
32+
#clock-cells = <0>;
33+
clock-frequency = <DT_FREQ_M(100)>;
34+
status = "disabled";
35+
};
36+
37+
clk_iso: clk_iso {
38+
compatible = "fixed-clock";
39+
#clock-cells = <0>;
40+
clock-frequency = <DT_FREQ_M(60)>;
41+
status = "disabled";
42+
};
43+
44+
clk_inro: clk_inro {
45+
compatible = "fixed-clock";
46+
#clock-cells = <0>;
47+
clock-frequency = <DT_FREQ_K(8)>;
48+
status = "disabled";
49+
};
50+
51+
clk_ibro: clk_ibro {
52+
compatible = "fixed-clock";
53+
#clock-cells = <0>;
54+
clock-frequency = <7372800>;
55+
status = "disabled";
56+
};
57+
58+
clk_ertco: clk_ertco {
59+
compatible = "fixed-clock";
60+
#clock-cells = <0>;
61+
clock-frequency = <32768>;
62+
status = "disabled";
63+
};
64+
65+
clk_erfo: clk_erfo {
66+
compatible = "fixed-clock";
67+
#clock-cells = <0>;
68+
clock-frequency = <DT_FREQ_M(32)>;
69+
status = "disabled";
70+
};
71+
};
72+
73+
soc {
74+
sram0: memory@20000000 {
75+
compatible = "mmio-sram";
76+
reg = <0x20000000 DT_SIZE_K(32)>;
77+
};
78+
79+
flc0: flash_controller@40029000 {
80+
compatible = "flash-controller";
81+
reg = <0x40029000 0x400>;
82+
83+
#address-cells = <1>;
84+
#size-cells = <1>;
85+
status = "okay";
86+
87+
flash0: flash@10000000 {
88+
compatible = "soc-nv-flash";
89+
reg = <0x10000000 DT_SIZE_K(512)>;
90+
write-block-size = <16>;
91+
erase-block-size = <8192>;
92+
};
93+
};
94+
95+
gcr: clock-controller@40000000 {
96+
reg = <0x40000000 0x400>;
97+
compatible = "adi,max32-gcr";
98+
#clock-cells = <2>;
99+
clocks = <&clk_ipo>;
100+
sysclk-prescaler = <1>;
101+
status = "okay";
102+
};
103+
104+
pinctrl: pin-controller@40008000 {
105+
compatible = "adi,max32-pinctrl";
106+
#address-cells = <1>;
107+
#size-cells = <1>;
108+
reg = <0x40008000 0x2000>;
109+
110+
gpio0: gpio@40008000 {
111+
reg = <0x40008000 0x1000>;
112+
compatible = "adi,max32-gpio";
113+
gpio-controller;
114+
#gpio-cells = <2>;
115+
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>;
116+
interrupts = <24 0>;
117+
status = "disabled";
118+
};
119+
120+
gpio1: gpio@40009000 {
121+
reg = <0x40009000 0x1000>;
122+
compatible = "adi,max32-gpio";
123+
gpio-controller;
124+
#gpio-cells = <2>;
125+
interrupts = <25 0>;
126+
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 1>;
127+
status = "disabled";
128+
};
129+
};
130+
131+
uart0: serial@40042000 {
132+
compatible = "adi,max32-uart";
133+
reg = <0x40042000 0x1000>;
134+
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>;
135+
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
136+
interrupts = <14 0>;
137+
status = "disabled";
138+
};
139+
140+
uart1: serial@40043000 {
141+
compatible = "adi,max32-uart";
142+
reg = <0x40043000 0x1000>;
143+
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 10>;
144+
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
145+
interrupts = <15 0>;
146+
status = "disabled";
147+
};
148+
149+
uart2: serial@40044000 {
150+
compatible = "adi,max32-uart";
151+
reg = <0x40044000 0x1000>;
152+
clocks = <&gcr ADI_MAX32_CLOCK_BUS1 1>;
153+
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
154+
interrupts = <34 0>;
155+
status = "disabled";
156+
};
157+
};
158+
};
159+
160+
&nvic {
161+
arm,num-irq-priority-bits = <3>;
162+
};

‎soc/adi/max32/CMakeLists.txt‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
# Copyright (c) 2023-2024 Analog Devices, Inc.
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
5+
zephyr_include_directories(common)
6+
zephyr_sources(soc.c)
7+
8+
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/adi/max32/Kconfig‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
# Analog Devices MAX32xxx MCU family
2+
3+
# Copyright (c) 2023-2024 Analog Devices, Inc.
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
config SOC_FAMILY_MAX32
7+
select ARM
8+
select CPU_HAS_ARM_MPU
9+
select CPU_HAS_FPU
10+
select CPU_CORTEX_M_HAS_SYSTICK
11+
select CLOCK_CONTROL
12+
select BUILD_OUTPUT_HEX
13+
14+
config SOC_MAX32690
15+
select CPU_CORTEX_M4
16+
17+
if SOC_FAMILY_MAX32
18+
19+
config MAX32_ON_ENTER_CPU_IDLE_HOOK
20+
bool "CPU idle hook enable"
21+
default y
22+
imply ARM_ON_ENTER_CPU_IDLE_HOOK
23+
help
24+
Enables a hook (z_arm_on_enter_cpu_idle()) that is called when
25+
the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
26+
If needed, this hook can be used to prevent the CPU from actually
27+
entering sleep by skipping the WFE/WFI instruction.
28+
29+
endif # SOC_FAMILY_MAX32

‎soc/adi/max32/Kconfig.defconfig‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
# Analog Devices MAX32xxx MCU family
2+
3+
# Copyright (c) 2023-2024 Analog Devices, Inc.
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
if SOC_FAMILY_MAX32
7+
8+
rsource "Kconfig.defconfig.max32*"
9+
10+
config SRAM_VECTOR_TABLE
11+
default y
12+
13+
endif # SOC_FAMILY_MAX32

‎soc/adi/max32/Kconfig.defconfig.max32690‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
# Analog Devices MAX32690 MCU
2+
3+
# Copyright (c) 2023-2024 Analog Devices, Inc.
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
if SOC_MAX32690
7+
8+
config SYS_CLOCK_HW_CYCLES_PER_SEC
9+
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
10+
11+
config NUM_IRQS
12+
default 112
13+
14+
endif # SOC_MAX32690

‎soc/adi/max32/Kconfig.soc‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
# Analog Devices MAX32xxx MCU family
2+
3+
# Copyright (c) 2023-2024 Analog Devices, Inc.
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
config SOC_FAMILY_MAX32
7+
bool
8+
9+
config SOC_FAMILY
10+
default "max32" if SOC_FAMILY_MAX32
11+
12+
config SOC_MAX32690
13+
bool
14+
select SOC_FAMILY_MAX32
15+
16+
config SOC_MAX32690_M4
17+
bool
18+
select SOC_MAX32690
19+
20+
config SOC
21+
default "max32690" if SOC_MAX32690

0 commit comments

Comments
 (0)