Merge branch 'main' into add_stm32u3c5_soc

Author: filipembedded

MAINTAINERS.yml

@@ -777,6 +777,7 @@ Bouffalolab Platforms:
     - VynDragon
   collaborators:
     - josuah
+    - will-tm
   files:
     - boards/aithinker/ai_*/
     - boards/bflb/
@@ -1332,6 +1333,7 @@ Documentation Infrastructure:
     - lgirdwood
     - kv2019i
     - TomasBarakNXP
+    - Peterson-Brett
   files:
     - drivers/audio/
     - include/zephyr/audio/
@@ -1921,6 +1923,7 @@ Documentation Infrastructure:
   collaborators:
     - TomasBarakNXP
     - anangl
+    - Peterson-Brett
   files:
     - doc/hardware/peripherals/audio/i2s.rst
     - drivers/i2s/
@@ -2985,6 +2988,7 @@ Infineon Platforms:
     - talih0
     - billwatersiii
     - jsbatch
+    - Peterson-Brett
   files:
     - boards/cypress/
     - boards/infineon/
@@ -4633,7 +4637,23 @@ Realtek Ameba Platforms:
     - dts/arm/realtek/ameba*/
     - dts/bindings/*/*ameba*
   labels:
-    - "platform: Ameba"
+    - "platform: Realtek Ameba"
+
+Realtek Bee Platforms:
+  status: maintained
+  maintainers:
+    - ZhiyuanTang17
+  files:
+    - boards/realtek/rtl87x2g*/
+    - boards/realtek/rtl8752h*/
+    - drivers/*/*bee*
+    - dts/arm/realtek/bee/
+    - dts/bindings/*/*bee*
+    - soc/realtek/bee/
+    - tests/boards/realtek/
+    - modules/hal_realtek/bee/
+  labels:
+    - "platform: Realtek Bee"
 
 Realtek EC Platforms:
   status: maintained
@@ -5893,6 +5913,7 @@ West:
     - VynDragon
   collaborators:
     - josuah
+    - will-tm
   files:
     - modules/hal_bouffalolab/
   labels:
@@ -5959,6 +5980,7 @@ West:
     - mcatee-infineon
     - billwatersiii
     - jsbatch
+    - Peterson-Brett
   files:
     - modules/Kconfig.infineon
     - modules/hal_infineon/

arch/mips/core/CMakeLists.txt

@@ -14,3 +14,5 @@ zephyr_library_sources(
 )
 
 zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
+
+zephyr_linker_sources(NOINIT noinit.ld)

arch/mips/core/noinit.ld

@@ -0,0 +1,10 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2026 Intel Corporation
+ */
+#ifdef CONFIG_LLEXT
+*(.llext_heap)
+*(.llext_ext_heap)
+*(.llext_metadata_heap)
+#endif /* CONFIG_LLEXT */

arch/riscv/Kconfig

@@ -19,6 +19,17 @@ config FLOAT_HARD
 	  This option enables the hard-float calling convention.
 	  Adds eight floating-point argument registers.
 
+config RISCV_USE_MSAVE_RESTORE
+	bool "Compile with -msave-restore to reduce some code footprint"
+	help
+	  The `-msave-restore` option enables the compiler to emit calls to library
+	  routines `__riscv_save_X` and `__riscv_restore_X` for preserving the
+	  callee-saved registers instead of inlining them in every function. This
+	  can reduce code size in some large functions. However, it introduces extra
+	  branching overhead, which may impact the performance in hot paths.
+
+	  If supported by your SoC, the `Zcmp` ISA extension should be preferred.
+
 choice RISCV_GP_PURPOSE
 	prompt "Purpose of the global pointer (GP) register"
 	default RISCV_GP if RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

arch/riscv/core/pmp.c

@@ -669,7 +669,7 @@ void z_riscv_pmp_init(void)
 	attr_cnt = set_pmp_mem_attr(&index, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 #endif /* CONFIG_MEM_ATTR */
 
-#if defined(CONFIG_MEM_ATTR) || defined(CONFIG_PMP_NO_LOCK_GLOBAL)
+#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
 	/*
 	 * This early, we want to protect unlock PMP entries as soon as
 	 * possible. But we need a temporary default "catch all" PMP entry for

arch/sparc/core/CMakeLists.txt

@@ -19,3 +19,5 @@ zephyr_library_sources_ifdef(CONFIG_SPARC_SVT trap_table_svt.S)
 zephyr_library_sources_ifndef(CONFIG_SPARC_SVT trap_table_mvt.S)
 zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
 zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
+
+zephyr_linker_sources(NOINIT noinit.ld)

arch/sparc/core/noinit.ld

@@ -0,0 +1,10 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2026 Intel Corporation
+ */
+#ifdef CONFIG_LLEXT
+*(.llext_heap)
+*(.llext_ext_heap)
+*(.llext_metadata_heap)
+#endif /* CONFIG_LLEXT */

boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_safe_overclock.dts

@@ -9,9 +9,9 @@
 #include "ai_m61_32s.dtsi"
 #include "ai_m61_32s_kit_common.dtsi"
 
-&clk_root {
-	/* Increased PLL speed used as FCLK */
-	clocks = <&clk_wifipll BL61X_WIFIPLL_OC_480MHz>;
+&clk_wifipll {
+	/* Increased PLL top output frequency to 480 MHz */
+	top-frequency = <BL61X_WIFIPLL_TOP_FREQ_OC1>;
 };
 
 &clk_bclk {

boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_unsafe_overclock.dts

@@ -9,9 +9,9 @@
 #include "ai_m61_32s.dtsi"
 #include "ai_m61_32s_kit_common.dtsi"
 
-&clk_root {
-	/* Increased PLL speed used as FCLK */
-	clocks = <&clk_wifipll BL61X_WIFIPLL_OCMAX_640MHz>;
+&clk_wifipll {
+	/* Increased PLL top output frequency to 640MHz */
+	top-frequency = <BL61X_WIFIPLL_TOP_FREQ_OC2>;
 };
 
 &reg_soc {

boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.yaml

@@ -26,4 +26,5 @@ supported:
   - adc
   - entropy
   - crypto
+  - counter
 vendor: bflb