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talih0carlescufi
talih0
authored and
carlescufi
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driver: pintcrl: xmc4xxx: Revert recent changes from i2c driver
In commit 541482f the pinctrl alternate function mask was increased to also include open-drain setting. Revert this change because open-drain can already be set via property drive-open-drain. The commit also added separate pinctrl nodes for the i2c controller and target modes. However, the alternate function settings is the same in both modes, so keep only one and remove the mode label. Signed-off-by: Andriy Gelman <[email protected]>
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-113
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+112
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‎boards/arm/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,12 +56,14 @@
5656
hwctrl = "disabled";
5757
};
5858

59-
&i2c_controller_scl_p0_13_u1c1 {
59+
&i2c_scl_p0_13_u1c1 {
6060
drive-strength = "strong-sharp-edge";
61+
drive-open-drain;
6162
hwctrl = "disabled";
6263
};
6364

64-
&i2c_controller_sda_p3_15_u1c1 {
65+
&i2c_sda_p3_15_u1c1 {
6566
drive-strength = "strong-soft-edge";
67+
drive-open-drain;
6668
hwctrl = "disabled";
6769
};

‎boards/arm/xmc47_relax_kit/xmc47_relax_kit.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@
134134
compatible = "infineon,xmc4xxx-i2c";
135135
status = "okay";
136136

137-
pinctrl-0 = <&i2c_controller_scl_p0_13_u1c1 &i2c_controller_sda_p3_15_u1c1>;
137+
pinctrl-0 = <&i2c_scl_p0_13_u1c1 &i2c_sda_p3_15_u1c1>;
138138
pinctrl-names = "default";
139139
scl-src = "DX1B";
140140
sda-src = "DX0A";

‎dts/arm/infineon/xmc4700_F144x2048-pinctrl.dtsi

Lines changed: 49 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -594,125 +594,78 @@
594594
hwctrl = "periph2";
595595
};
596596

597-
/omit-if-no-ref/ i2c_controller_scl_p0_8_u0c0: i2c_controller_scl_p0_8_u0c0 {
598-
pinmux = <XMC4XXX_PINMUX_SET(0, 8, 0x1A)>;
597+
/omit-if-no-ref/ i2c_sda_p4_7_u2c1: i2c_sda_p4_7_u2c1 {
598+
pinmux = <XMC4XXX_PINMUX_SET(4, 7, 1)>; /* USIC sda-src = DX0C */
599599
};
600-
/omit-if-no-ref/ i2c_controller_scl_p1_1_u0c0: i2c_controller_scl_p1_1_u0c0 {
601-
pinmux = <XMC4XXX_PINMUX_SET(1, 1, 0x1A)>;
600+
/omit-if-no-ref/ i2c_sda_p5_1_u0c0: i2c_sda_p5_1_u0c0 {
601+
pinmux = <XMC4XXX_PINMUX_SET(5, 1, 1)>; /* USIC sda-src = DX0A */
602602
};
603-
/omit-if-no-ref/ i2c_controller_scl_p2_4_u0c1: i2c_controller_scl_p2_4_u0c1 {
604-
pinmux = <XMC4XXX_PINMUX_SET(2, 4, 0x1A)>;
603+
/omit-if-no-ref/ i2c_sda_p3_13_u0c1: i2c_sda_p3_13_u0c1 {
604+
pinmux = <XMC4XXX_PINMUX_SET(3, 13, 2)>; /* USIC sda-src = DX0D */
605605
};
606-
/omit-if-no-ref/ i2c_controller_scl_p3_0_u0c1: i2c_controller_scl_p3_0_u0c1 {
607-
pinmux = <XMC4XXX_PINMUX_SET(3, 0, 0x1A)>;
606+
/omit-if-no-ref/ i2c_sda_p3_5_u0c1: i2c_sda_p3_5_u0c1 {
607+
pinmux = <XMC4XXX_PINMUX_SET(3, 5, 4)>; /* USIC sda-src = DX0A */
608608
};
609-
/omit-if-no-ref/ i2c_controller_scl_p6_2_u0c1: i2c_controller_scl_p6_2_u0c1 {
610-
pinmux = <XMC4XXX_PINMUX_SET(6, 2, 0x1A)>;
609+
/omit-if-no-ref/ i2c_sda_p2_14_u1c0: i2c_sda_p2_14_u1c0 {
610+
pinmux = <XMC4XXX_PINMUX_SET(2, 14, 2)>; /* USIC sda-src = DX0D */
611611
};
612-
/omit-if-no-ref/ i2c_controller_scl_p0_11_u1c0: i2c_controller_scl_p0_11_u1c0 {
613-
pinmux = <XMC4XXX_PINMUX_SET(0, 11, 0x1A)>;
612+
/omit-if-no-ref/ i2c_sda_p0_5_u1c0: i2c_sda_p0_5_u1c0 {
613+
pinmux = <XMC4XXX_PINMUX_SET(0, 5, 2)>; /* USIC sda-src = DX0B */
614614
};
615-
/omit-if-no-ref/ i2c_controller_scl_p5_8_u1c0: i2c_controller_scl_p5_8_u1c0 {
616-
pinmux = <XMC4XXX_PINMUX_SET(5, 8, 0x1A)>;
615+
/omit-if-no-ref/ i2c_sda_p4_2_u1c1: i2c_sda_p4_2_u1c1 {
616+
pinmux = <XMC4XXX_PINMUX_SET(4, 2, 2)>; /* USIC sda-src = DX0C */
617617
};
618-
/omit-if-no-ref/ i2c_controller_scl_p0_10_u1c1: i2c_controller_scl_p0_10_u1c1 {
619-
pinmux = <XMC4XXX_PINMUX_SET(0, 10, 0x1A)>;
618+
/omit-if-no-ref/ i2c_sda_p5_0_u2c0: i2c_sda_p5_0_u2c0 {
619+
pinmux = <XMC4XXX_PINMUX_SET(5, 0, 1)>; /* USIC sda-src = DX0B */
620620
};
621-
/omit-if-no-ref/ i2c_controller_scl_p0_13_u1c1: i2c_controller_scl_p0_13_u1c1 {
622-
pinmux = <XMC4XXX_PINMUX_SET(0, 13, 0x1A)>;
621+
/omit-if-no-ref/ i2c_sda_p1_5_u0c0: i2c_sda_p1_5_u0c0 {
622+
pinmux = <XMC4XXX_PINMUX_SET(1, 5, 2)>; /* USIC sda-src = DX0A */
623623
};
624-
/omit-if-no-ref/ i2c_controller_scl_p5_2_u2c0: i2c_controller_scl_p5_2_u2c0 {
625-
pinmux = <XMC4XXX_PINMUX_SET(5, 2, 0x1A)>;
624+
/omit-if-no-ref/ i2c_sda_p2_5_u0c1: i2c_sda_p2_5_u0c1 {
625+
pinmux = <XMC4XXX_PINMUX_SET(2, 5, 2)>; /* USIC sda-src = DX0B */
626626
};
627-
/omit-if-no-ref/ i2c_controller_scl_p3_6_u2c1: i2c_controller_scl_p3_6_u2c1 {
628-
pinmux = <XMC4XXX_PINMUX_SET(3, 6, 0x1A)>;
627+
/omit-if-no-ref/ i2c_sda_p3_15_u1c1: i2c_sda_p3_15_u1c1 {
628+
pinmux = <XMC4XXX_PINMUX_SET(3, 15, 2)>; /* USIC sda-src = DX0A */
629629
};
630-
/omit-if-no-ref/ i2c_controller_sda_p1_5_u0c0: i2c_controller_sda_p1_5_u0c0 {
631-
pinmux = <XMC4XXX_PINMUX_SET(1, 5, 0x1A)>;
632-
};
633-
/omit-if-no-ref/ i2c_controller_sda_p2_5_u0c1: i2c_controller_sda_p2_5_u0c1 {
634-
pinmux = <XMC4XXX_PINMUX_SET(2, 5, 0x1A)>;
635-
};
636-
/omit-if-no-ref/ i2c_controller_sda_p3_13_u0c1: i2c_controller_sda_p3_13_u0c1 {
637-
pinmux = <XMC4XXX_PINMUX_SET(3, 13, 0x1A)>;
638-
};
639-
/omit-if-no-ref/ i2c_controller_sda_p0_5_u1c0: i2c_controller_sda_p0_5_u1c0 {
640-
pinmux = <XMC4XXX_PINMUX_SET(0, 5, 0x1A)>;
641-
};
642-
/omit-if-no-ref/ i2c_controller_sda_p2_14_u1c0: i2c_controller_sda_p2_14_u1c0 {
643-
pinmux = <XMC4XXX_PINMUX_SET(2, 14, 0x1A)>;
644-
};
645-
/omit-if-no-ref/ i2c_controller_sda_p3_15_u1c1: i2c_controller_sda_p3_15_u1c1 {
646-
pinmux = <XMC4XXX_PINMUX_SET(3, 15, 0x1A)>;
647-
};
648-
/omit-if-no-ref/ i2c_controller_sda_p4_2_u1c1: i2c_controller_sda_p4_2_u1c1 {
649-
pinmux = <XMC4XXX_PINMUX_SET(4, 2, 0x1A)>;
650-
};
651-
/omit-if-no-ref/ i2c_controller_sda_p5_0_u2c0: i2c_controller_sda_p5_0_u2c0 {
652-
pinmux = <XMC4XXX_PINMUX_SET(5, 0, 0x1A)>;
653-
};
654-
/omit-if-no-ref/ i2c_controller_sda_p3_5_u2c1: i2c_controller_sda_p3_5_u2c1 {
655-
pinmux = <XMC4XXX_PINMUX_SET(3, 5, 0x1A)>;
656-
};
657-
/omit-if-no-ref/ i2c_target_scl_p0_8_u0c0: i2c_target_scl_p0_8_u0c0 {
658-
pinmux = <XMC4XXX_PINMUX_SET(0, 8, 0x19)>;
659-
};
660-
/omit-if-no-ref/ i2c_target_scl_p1_1_u0c0: i2c_target_scl_p1_1_u0c0 {
661-
pinmux = <XMC4XXX_PINMUX_SET(1, 1, 0x19)>;
662-
};
663-
/omit-if-no-ref/ i2c_target_scl_p2_4_u0c1: i2c_target_scl_p2_4_u0c1 {
664-
pinmux = <XMC4XXX_PINMUX_SET(2, 4, 0x19)>;
665-
};
666-
/omit-if-no-ref/ i2c_target_scl_p3_0_u0c1: i2c_target_scl_p3_0_u0c1 {
667-
pinmux = <XMC4XXX_PINMUX_SET(3, 0, 0x19)>;
668-
};
669-
/omit-if-no-ref/ i2c_target_scl_p6_2_u0c1: i2c_target_scl_p6_2_u0c1 {
670-
pinmux = <XMC4XXX_PINMUX_SET(6, 2, 0x19)>;
671-
};
672-
/omit-if-no-ref/ i2c_target_scl_p0_11_u1c0: i2c_target_scl_p0_11_u1c0 {
673-
pinmux = <XMC4XXX_PINMUX_SET(0, 11, 0x19)>;
674-
};
675-
/omit-if-no-ref/ i2c_target_scl_p5_8_u1c0: i2c_target_scl_p5_8_u1c0 {
676-
pinmux = <XMC4XXX_PINMUX_SET(5, 8, 0x19)>;
677-
};
678-
/omit-if-no-ref/ i2c_target_scl_p0_10_u1c1: i2c_target_scl_p0_10_u1c1 {
679-
pinmux = <XMC4XXX_PINMUX_SET(0, 10, 0x19)>;
630+
631+
/omit-if-no-ref/ i2c_scl_p5_2_u2c0: i2c_scl_p5_2_u2c0 {
632+
pinmux = <XMC4XXX_PINMUX_SET(5, 2, 1)>; /* USIC scl-src = DX1A */
680633
};
681-
/omit-if-no-ref/ i2c_target_scl_p0_13_u1c1: i2c_target_scl_p0_13_u1c1 {
682-
pinmux = <XMC4XXX_PINMUX_SET(0, 13, 0x19)>;
634+
/omit-if-no-ref/ i2c_scl_p3_6_u0c1: i2c_scl_p3_6_u0c1 {
635+
pinmux = <XMC4XXX_PINMUX_SET(3, 6, 4)>; /* USIC scl-src = DX1B */
683636
};
684-
/omit-if-no-ref/ i2c_target_scl_p5_2_u2c0: i2c_target_scl_p5_2_u2c0 {
685-
pinmux = <XMC4XXX_PINMUX_SET(5, 2, 0x19)>;
637+
/omit-if-no-ref/ i2c_scl_p6_2_u0c1: i2c_scl_p6_2_u0c1 {
638+
pinmux = <XMC4XXX_PINMUX_SET(6, 2, 2)>; /* USIC scl-src = DX1C */
686639
};
687-
/omit-if-no-ref/ i2c_target_scl_p3_6_u2c1: i2c_target_scl_p3_6_u2c1 {
688-
pinmux = <XMC4XXX_PINMUX_SET(3, 6, 0x19)>;
640+
/omit-if-no-ref/ i2c_scl_p1_1_u0c0: i2c_scl_p1_1_u0c0 {
641+
pinmux = <XMC4XXX_PINMUX_SET(1, 1, 2)>; /* USIC scl-src = DX1A */
689642
};
690-
/omit-if-no-ref/ i2c_target_sda_p1_5_u0c0: i2c_target_sda_p1_5_u0c0 {
691-
pinmux = <XMC4XXX_PINMUX_SET(1, 5, 0x19)>;
643+
/omit-if-no-ref/ i2c_scl_p3_0_u0c1: i2c_scl_p3_0_u0c1 {
644+
pinmux = <XMC4XXX_PINMUX_SET(3, 0, 2)>; /* USIC scl-src = DX1B */
692645
};
693-
/omit-if-no-ref/ i2c_target_sda_p2_5_u0c1: i2c_target_sda_p2_5_u0c1 {
694-
pinmux = <XMC4XXX_PINMUX_SET(2, 5, 0x19)>;
646+
/omit-if-no-ref/ i2c_scl_p5_8_u1c0: i2c_scl_p5_8_u1c0 {
647+
pinmux = <XMC4XXX_PINMUX_SET(5, 8, 2)>; /* USIC scl-src = DX1B */
695648
};
696-
/omit-if-no-ref/ i2c_target_sda_p3_13_u0c1: i2c_target_sda_p3_13_u0c1 {
697-
pinmux = <XMC4XXX_PINMUX_SET(3, 13, 0x19)>;
649+
/omit-if-no-ref/ i2c_scl_p4_0_u1c0: i2c_scl_p4_0_u1c0 {
650+
pinmux = <XMC4XXX_PINMUX_SET(4, 0, 4)>; /* USIC scl-src = DX1C */
698651
};
699-
/omit-if-no-ref/ i2c_target_sda_p0_5_u1c0: i2c_target_sda_p0_5_u1c0 {
700-
pinmux = <XMC4XXX_PINMUX_SET(0, 5, 0x19)>;
652+
/omit-if-no-ref/ i2c_scl_p2_4_u0c1: i2c_scl_p2_4_u0c1 {
653+
pinmux = <XMC4XXX_PINMUX_SET(2, 4, 2)>; /* USIC scl-src = DX1A */
701654
};
702-
/omit-if-no-ref/ i2c_target_sda_p2_14_u1c0: i2c_target_sda_p2_14_u1c0 {
703-
pinmux = <XMC4XXX_PINMUX_SET(2, 14, 0x19)>;
655+
/omit-if-no-ref/ i2c_scl_p0_11_u1c0: i2c_scl_p0_11_u1c0 {
656+
pinmux = <XMC4XXX_PINMUX_SET(0, 11, 2)>; /* USIC scl-src = DX1A */
704657
};
705-
/omit-if-no-ref/ i2c_target_sda_p3_15_u1c1: i2c_target_sda_p3_15_u1c1 {
706-
pinmux = <XMC4XXX_PINMUX_SET(3, 15, 0x19)>;
658+
/omit-if-no-ref/ i2c_scl_p0_13_u1c1: i2c_scl_p0_13_u1c1 {
659+
pinmux = <XMC4XXX_PINMUX_SET(0, 13, 2)>; /* USIC scl-src = DX1B */
707660
};
708-
/omit-if-no-ref/ i2c_target_sda_p4_2_u1c1: i2c_target_sda_p4_2_u1c1 {
709-
pinmux = <XMC4XXX_PINMUX_SET(4, 2, 0x19)>;
661+
/omit-if-no-ref/ i2c_scl_p0_10_u1c1: i2c_scl_p0_10_u1c1 {
662+
pinmux = <XMC4XXX_PINMUX_SET(0, 10, 2)>; /* USIC scl-src = DX1A */
710663
};
711-
/omit-if-no-ref/ i2c_target_sda_p5_0_u2c0: i2c_target_sda_p5_0_u2c0 {
712-
pinmux = <XMC4XXX_PINMUX_SET(5, 0, 0x19)>;
664+
/omit-if-no-ref/ i2c_scl_p4_2_u2c1: i2c_scl_p4_2_u2c1 {
665+
pinmux = <XMC4XXX_PINMUX_SET(4, 2, 4)>; /* USIC scl-src = DX1A */
713666
};
714-
/omit-if-no-ref/ i2c_target_sda_p3_5_u2c1: i2c_target_sda_p3_5_u2c1 {
715-
pinmux = <XMC4XXX_PINMUX_SET(3, 5, 0x19)>;
667+
/omit-if-no-ref/ i2c_scl_p0_8_u0c0: i2c_scl_p0_8_u0c0 {
668+
pinmux = <XMC4XXX_PINMUX_SET(0, 8, 2)>; /* USIC scl-src = DX1B */
716669
};
717670

718671
/omit-if-no-ref/ pwm_out_p0_12_ccu40_ch3: pwm_out_p0_12_ccu40_ch3 {

‎dts/bindings/i2c/infineon,xmc4xxx-i2c.yaml

Lines changed: 43 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,49 @@
33
#
44
# SPDX-License-Identifier: Apache-2.0
55

6-
description: Infineon XMC4XXX I2C
6+
description: |
7+
8+
Infineon XMC4XXX I2C
9+
10+
This driver configures the USIC as an I2C device.
11+
12+
Example devicetree configuration with an adt7420 temperature sensor
13+
connected on the bus:
14+
15+
&usic1ch1 {
16+
compatible = "infineon,xmc4xxx-i2c";
17+
status = "okay";
18+
19+
pinctrl-0 = <&i2c_scl_p0_13_u1c1 &i2c_sda_p3_15_u1c1>;
20+
pinctrl-names = "default";
21+
scl-src = "DX1B";
22+
sda-src = "DX0A";
23+
interrupts = <94 1>;
24+
25+
#address-cells = <1>;
26+
#size-cells = <0>;
27+
28+
clock-frequency = <I2C_BITRATE_STANDARD>;
29+
adt7420@48 {
30+
compatible = "adi,adt7420";
31+
reg = <0x48>;
32+
};
33+
};
34+
35+
The pinctrl nodes need to be configured as open-drain and
36+
hwctrl should be disabled:
37+
38+
&i2c_scl_p0_13_u1c1 {
39+
drive-strength = "strong-sharp-edge";
40+
drive-open-drain;
41+
hwctrl = "disabled";
42+
};
43+
44+
&i2c_sda_p3_15_u1c1 {
45+
drive-strength = "strong-soft-edge";
46+
drive-open-drain;
47+
hwctrl = "disabled";
48+
};
749
850
compatible: "infineon,xmc4xxx-i2c"
951

‎include/zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -16,33 +16,33 @@
1616
#define XMC4XXX_PIN_MASK 0xf
1717

1818
#define XMC4XXX_ALT_POS 8
19-
#define XMC4XXX_ALT_MASK 0x1f
19+
#define XMC4XXX_ALT_MASK 0xf
2020

21-
#define XMC4XXX_PULL_DOWN_POS 13
21+
#define XMC4XXX_PULL_DOWN_POS 12
2222
#define XMC4XXX_PULL_DOWN_MASK 0x1
2323

24-
#define XMC4XXX_PULL_UP_POS 14
24+
#define XMC4XXX_PULL_UP_POS 13
2525
#define XMC4XXX_PULL_UP_MASK 0x1
2626

27-
#define XMC4XXX_PUSH_PULL_POS 15
27+
#define XMC4XXX_PUSH_PULL_POS 14
2828
#define XMC4XXX_PUSH_PULL_MASK 0x1
2929

30-
#define XMC4XXX_OPEN_DRAIN_POS 16
30+
#define XMC4XXX_OPEN_DRAIN_POS 15
3131
#define XMC4XXX_OPEN_DRAIN_MASK 0x1
3232

33-
#define XMC4XXX_OUT_HIGH_POS 17
33+
#define XMC4XXX_OUT_HIGH_POS 16
3434
#define XMC4XXX_OUT_HIGH_MASK 0x1
3535

36-
#define XMC4XXX_OUT_LOW_POS 18
36+
#define XMC4XXX_OUT_LOW_POS 17
3737
#define XMC4XXX_OUT_LOW_MASK 0x1
3838

39-
#define XMC4XXX_INV_INPUT_POS 19
39+
#define XMC4XXX_INV_INPUT_POS 18
4040
#define XMC4XXX_INV_INPUT_MASK 0x1
4141

42-
#define XMC4XXX_DRIVE_POS 20
42+
#define XMC4XXX_DRIVE_POS 19
4343
#define XMC4XXX_DRIVE_MASK 0x7
4444

45-
#define XMC4XXX_HWCTRL_POS 23
45+
#define XMC4XXX_HWCTRL_POS 22
4646
#define XMC4XXX_HWCTRL_MASK 0x3
4747

4848
/* Setters and getters */

‎tests/drivers/i2c/i2c_api/boards/xmc47_relax_kit.overlay

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,19 +11,21 @@
1111
};
1212
};
1313

14-
&i2c_controller_scl_p6_2_u0c1 {
14+
&i2c_scl_p6_2_u0c1 {
1515
drive-strength = "strong-sharp-edge";
16+
drive-open-drain;
1617
hwctrl = "disabled";
1718
};
1819

19-
&i2c_controller_sda_p3_13_u0c1 {
20+
&i2c_sda_p3_13_u0c1 {
2021
drive-strength = "strong-soft-edge";
22+
drive-open-drain;
2123
hwctrl = "disabled";
2224
};
2325

2426
&usic0ch1 {
2527
compatible = "infineon,xmc4xxx-i2c";
26-
pinctrl-0 = <&i2c_controller_scl_p6_2_u0c1 &i2c_controller_sda_p3_13_u0c1>;
28+
pinctrl-0 = <&i2c_scl_p6_2_u0c1 &i2c_sda_p3_13_u0c1>;
2729
pinctrl-names = "default";
2830
scl-src = "DX1C";
2931
sda-src = "DX0D";

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