arch: Added initial OpenRISC architecture port

This patch adds support for the OpenRISC 1000 (or1k) architecture: a
MIPS-like open hardware ISA which was first introduced in 2000.

The thread switching implementation uses the modern Zephyr thread "switch"
architecture.

Signed-off-by: Joel Holdsworth <[email protected]>

Author: jhol

MAINTAINERS.yml

@@ -5696,3 +5696,15 @@ zbus:
     - "area: llext"
   tests:
     - llext
+
+OpenRISC Arch:
+  status: maintained
+  maintainers:
+    - jhol
+  files:
+    - arch/openrisc/
+    - include/zephyr/arch/openrisc/
+  labels:
+    - "area: OpenRISC"
+  tests:
+    - arch.openrisc

arch/Kconfig

@@ -66,6 +66,16 @@ config MIPS
 	help
 	  MIPS architecture
 
+config OPENRISC
+	bool
+	select ARCH_IS_SET
+	select ATOMIC_OPERATIONS_BUILTIN
+	select BIG_ENDIAN
+	select USE_SWITCH
+	select USE_SWITCH_SUPPORTED
+	help
+	  OpenRISC architecture
+
 config SPARC
 	bool
 	select ARCH_IS_SET
@@ -227,7 +237,7 @@ config SRAM_BASE_ADDRESS
 	  /chosen/zephyr,sram in devicetree. The user should generally avoid
 	  changing it via menuconfig or in configuration files.
 
-if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV
+if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV || OPENRISC
 
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_FLASH := zephyr,flash
@@ -250,7 +260,7 @@ config FLASH_BASE_ADDRESS
 	  normally set by the board's defconfig file and the user should generally
 	  avoid modifying it via the menu configuration.
 
-endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV
+endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV || OPENRISC
 
 if ARCH_HAS_TRUSTED_EXECUTION
 

arch/archs.yml

@@ -9,6 +9,8 @@ archs:
     path: mips
   - name: nios2
     path: nios2
+  - name: openrisc
+    path: openrisc
   - name: posix
     path: posix
   - name: riscv

arch/openrisc/CMakeLists.txt

@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <[email protected]>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-or1k")
+
+add_subdirectory(core)
+zephyr_include_directories(include)

arch/openrisc/Kconfig

@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <[email protected]>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menu "OpenRISC Options"
+	depends on OPENRISC
+
+config ARCH
+	string
+	default "openrisc"
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config GEN_SW_ISR_TABLE
+	default y
+
+config NUM_IRQS
+	int
+
+endmenu

arch/openrisc/core/CMakeLists.txt

@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <[email protected]>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+
+zephyr_library_sources(
+  cpu_idle.c
+  exception.S
+  fatal.c
+  irq_manage.c
+  irq_offload.c
+  prep_c.c
+  reboot.c
+  switch.S
+  thread.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)

arch/openrisc/core/asm_macros.inc

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation
+ *
+ * Convenience macros for assembly code
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Convenience macros for assembly code. */
+
+
+/*
+ * Helper macro which stores the value of a register to a the address contained
+ * in a pointer register plus an immediate offset.
+ */
+
+.macro op_store_reg reg, off, ptr_reg
+	l.sw \off(\ptr_reg), \reg
+.endm
+
+
+/*
+ * Helper macro which loads a value to a register from an address contained in
+ * a pointer register plus an immediate offset.
+ */
+
+.macro op_load_reg reg, off, ptr_reg
+	l.lwz \reg, \off(\ptr_reg)
+.endm

arch/openrisc/core/cpu_idle.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/irq.h>
+
+#include <zephyr/tracing/tracing.h>
+
+#include <openrisc/openriscregs.h>
+
+static ALWAYS_INLINE void openrisc_idle(unsigned int key)
+{
+	sys_trace_idle();
+
+	/* unlock interrupts */
+	irq_unlock(key);
+
+	/* wait for interrupt */
+	if (openrisc_read_spr(SPR_UPR) & SPR_UPR_PMP) {
+		openrisc_write_spr(SPR_PMR, openrisc_read_spr(SPR_PMR) | SPR_PMR_DME);
+	}
+}
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
+void arch_cpu_idle(void)
+{
+	openrisc_idle(1);
+}
+#endif
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+void arch_cpu_atomic_idle(unsigned int key)
+{
+	openrisc_idle(key);
+}
+#endif