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lines changed Original file line number Diff line number Diff line change 11/* SoC level DTS fixup file */
22
33/* CCM configuration */
4- #define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
5- #define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
4+ #define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
5+ #define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
66
7- #define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_0_BASE_ADDRESS
8- #define DT_ICCM_SIZE (DT_ARC_ICCM_0_SIZE >> 10)
7+ #define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_0_BASE_ADDRESS
8+ #define DT_ICCM_SIZE (DT_ARC_ICCM_0_SIZE >> 10)
9+
10+ #define DT_DDR_BASE_ADDRESS DT_MMIO_SRAM_10000000_BASE_ADDRESS
11+ #define DT_DDR_SIZE (DT_MMIO_SRAM_10000000_SIZE >> 10)
912
1013/*
1114 * UART configuration
Original file line number Diff line number Diff line change 1717 * DRAM includes the exception vector table at reset, which is at
1818 * the beginning of the region.
1919 */
20- #if defined(DT_MMIO_SRAM_0_BASE_ADDRESS ) && (DT_MMIO_SRAM_0_SIZE > 0)
21- #define SRAM_START DT_MMIO_SRAM_0_BASE_ADDRESS
22- #define SRAM_SIZE ( DT_MMIO_SRAM_0_SIZE >> 10 )
20+ #if defined(DT_DDR_BASE_ADDRESS ) && (DT_DDR_SIZE > 0)
21+ #define SRAM_START DT_DDR_BASE_ADDRESS
22+ #define SRAM_SIZE DT_DDR_SIZE
2323#endif
2424
2525/* Instruction Closely Coupled Memory (ICCM) base address and size */
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