soc: arm: stm32g4 add rtc feature on this serie

This patch enables the rtc clock on the stm32g4 soc
from STMicroelectronics.
Even if the set by default (reset value of theRCC_APB1ENR)
the bit is marked as 1.

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

drivers/clock_control/clock_stm32g4.c

@@ -46,12 +46,12 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
  */
 void config_enable_default_clocks(void)
 {
-#ifdef CONFIG_CLOCK_STM32_LSE
-	/* LSE belongs to the back-up domain, enable access.*/
-
 	/* Enable the power interface clock */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 
+#ifdef CONFIG_CLOCK_STM32_LSE
+	/* LSE belongs to the back-up domain, enable access.*/
+
 	/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
 	LL_PWR_EnableBkUpAccess();
 	while (!LL_PWR_IsEnabledBkUpAccess()) {

dts/arm/st/g4/stm32g4.dtsi

@@ -486,7 +486,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
 			prescaler = <32768>;
 			status = "disabled";
 			label = "RTC_0";