soc: arm: add GD32F4xx serial SoCs definition

Add GD32F4xx serial SoCs, Gd32F405, GD32F407 and GD32F450.

Signed-off-by: HaiLong Yang <[email protected]>

Author: cameled

soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f405

@@ -0,0 +1,21 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_GD32F405R || SOC_GD32F405V || SOC_GD32F405Z
+
+config SOC
+	default	"gd32f405r" if SOC_GD32F405R
+	default	"gd32f405v" if SOC_GD32F405V
+	default	"gd32f405z" if SOC_GD32F405Z
+
+config SOC_SERIES_GD32F405
+	bool
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 168000000
+
+config NUM_IRQS
+	default 82
+
+endif

soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f407

@@ -0,0 +1,21 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_GD32F407R || SOC_GD32F407V || SOC_GD32F407Z
+
+config SOC
+	default	"gd32f407r" if SOC_GD32F407R
+	default	"gd32f407v" if SOC_GD32F407V
+	default	"gd32f407z" if SOC_GD32F407Z
+
+config SOC_SERIES_GD32F407
+	bool
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 168000000
+
+config NUM_IRQS
+	default 82
+
+endif

soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f450

@@ -0,0 +1,21 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_GD32F450V || SOC_GD32F450Z || SOC_GD32F450I
+
+config SOC
+	default	"gd32f450v" if SOC_GD32F450V
+	default	"gd32f450z" if SOC_GD32F450Z
+	default	"gd32f450i" if SOC_GD32F450I
+
+config SOC_SERIES_GD32F450
+	bool
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 200000000
+
+config NUM_IRQS
+	default 91
+
+endif

soc/arm/gigadevice/gd32f4/Kconfig.soc

@@ -1,4 +1,5 @@
 # Copyright (c) 2021, ATL Electronics
+# Copyright (c) 2021 BrainCo Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 choice
@@ -14,4 +15,31 @@ choice
 	config SOC_GD32F403Z
 		bool "gd32f403z"
 
+	config SOC_GD32F405R
+		bool "gd32f405r"
+
+	config SOC_GD32F405V
+		bool "gd32f405v"
+
+	config SOC_GD32F405Z
+		bool "gd32f405z"
+
+	config SOC_GD32F407R
+		bool "gd32f407r"
+
+	config SOC_GD32F407V
+		bool "gd32f407v"
+
+	config SOC_GD32F407Z
+		bool "gd32f407z"
+
+	config SOC_GD32F450V
+		bool "gd32f450v"
+
+	config SOC_GD32F450Z
+		bool "gd32f450z"
+
+	config SOC_GD32F450I
+		bool "gd32f450i"
+
 endchoice

soc/arm/gigadevice/gd32f4/soc.h

@@ -22,6 +22,10 @@
 
 #if defined(CONFIG_SOC_SERIES_GD32F403)
 #include <gd32f403.h>
+#elif defined(CONFIG_SOC_SERIES_GD32F405) || \
+	  defined(CONFIG_SOC_SERIES_GD32F407) || \
+	  defined(CONFIG_SOC_SERIES_GD32F450)
+#include <gd32f4xx.h>
 #else
 #error Library does not support the specified device.
 #endif