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maass-hamburgcarlescufi
maass-hamburg
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carlescufi
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drivers: spi: litex: add litespi driver
add litespi driver for flash. Signed-off-by: Fin Maaß <[email protected]>
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‎drivers/spi/CMakeLists.txt‎

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@@ -25,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_NRFX_SPIM spi_nrfx_spim.c
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spi_nrfx_common.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_NRFX_SPIS spi_nrfx_spis.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_LITEX spi_litex.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_LITEX_LITESPI spi_litex_litespi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_OC_SIMPLE spi_oc_simple.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI spi_xec_qmspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_GECKO spi_gecko.c)

‎drivers/spi/Kconfig.litex‎

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@@ -9,3 +9,10 @@ config SPI_LITEX
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depends on DT_HAS_LITEX_SPI_ENABLED
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help
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Enable the SPI peripherals on LiteX
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config SPI_LITEX_LITESPI
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bool "LiteX SPI LiteSPI controller driver"
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default y
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depends on DT_HAS_LITEX_SPI_LITESPI_ENABLED
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help
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Enable the SPI peripherals on LiteX

‎drivers/spi/spi_litex_litespi.c‎

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/*
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* Copyright (c) 2024 Vogl Electronic GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT litex_spi_litespi
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_litex_litespi);
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#include <zephyr/sys/byteorder.h>
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#include "spi_litex_common.h"
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#define SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET 0x0
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#define SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
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#define SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET 0x2
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#define SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET 0x0
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#define SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET 0x1
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#define SPI_MAX_WORD_SIZE 32
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#define SPI_MAX_CS_SIZE 4
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struct spi_litex_dev_config {
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uint32_t core_mmap_dummy_bits_addr;
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uint32_t core_master_cs_addr;
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uint32_t core_master_phyconfig_addr;
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uint32_t core_master_rxtx_addr;
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uint32_t core_master_rxtx_size;
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uint32_t core_master_status_addr;
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uint32_t phy_clk_divisor_addr;
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bool phy_clk_divisor_exists;
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};
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struct spi_litex_data {
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struct spi_context ctx;
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uint8_t dfs; /* dfs in bytes: 1,2 or 4 */
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};
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static int spi_litex_set_frequency(const struct device *dev, const struct spi_config *config)
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{
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const struct spi_litex_dev_config *dev_config = dev->config;
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if (!dev_config->phy_clk_divisor_exists) {
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/* In the LiteX Simulator the phy_clk_divisor doesn't exists, thats why we check. */
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LOG_WRN("No phy_clk_divisor found, can't change frequency");
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return 0;
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}
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uint32_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), (2 * config->frequency)) - 1;
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litex_write32(divisor, dev_config->phy_clk_divisor_addr);
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return 0;
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}
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/* Helper Functions */
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static int spi_config(const struct device *dev, const struct spi_config *config)
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{
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struct spi_litex_data *dev_data = dev->data;
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if (config->slave != 0) {
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if (config->slave >= SPI_MAX_CS_SIZE) {
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LOG_ERR("More slaves than supported");
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return -ENOTSUP;
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}
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}
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if (config->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (SPI_WORD_SIZE_GET(config->operation) > SPI_MAX_WORD_SIZE) {
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LOG_ERR("Word size must be <= %d, is %d", SPI_MAX_WORD_SIZE,
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SPI_WORD_SIZE_GET(config->operation));
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return -ENOTSUP;
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}
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if (config->operation & SPI_CS_ACTIVE_HIGH) {
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LOG_ERR("CS active high not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_LOCK_ON) {
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LOG_ERR("Lock On not supported");
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return -ENOTSUP;
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}
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if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
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(config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only supports single mode");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return -ENOTSUP;
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}
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if (config->operation & (SPI_MODE_CPOL | SPI_MODE_CPHA)) {
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LOG_ERR("Only supports CPOL=CPHA=0");
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return -ENOTSUP;
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}
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if (config->operation & SPI_OP_MODE_SLAVE) {
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode not supported");
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return -ENOTSUP;
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}
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dev_data->dfs = get_dfs_value(config);
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spi_litex_set_frequency(dev, config);
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return 0;
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}
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static void spiflash_len_mask_width_write(uint32_t len, uint32_t width, uint32_t mask,
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uint32_t addr)
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{
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uint32_t tmp = len & BIT_MASK(8);
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uint32_t word = tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET * 8);
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tmp = width & BIT_MASK(8);
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word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET * 8);
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tmp = mask & BIT_MASK(8);
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word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET * 8);
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litex_write32(word, addr);
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}
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static int spi_litex_xfer(const struct device *dev, const struct spi_config *config)
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{
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const struct spi_litex_dev_config *dev_config = dev->config;
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struct spi_litex_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t txd, rxd;
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int ret = 0;
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uint8_t len = data->dfs; /* SPI Xfer length*/
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uint8_t old_len = len; /* old SPI Xfer length*/
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uint8_t width = BIT(0); /* SPI Xfer width*/
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uint8_t mask = BIT(0); /* SPI Xfer mask*/
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spiflash_len_mask_width_write(len * 8, width, mask, dev_config->core_master_phyconfig_addr);
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litex_write32(BIT(config->slave), dev_config->core_master_cs_addr);
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do {
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len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->core_master_rxtx_size);
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if (len != old_len) {
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spiflash_len_mask_width_write(len * 8, width, mask,
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dev_config->core_master_phyconfig_addr);
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old_len = len;
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}
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if (spi_context_tx_buf_on(ctx)) {
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litex_spi_tx_put(len, &txd, ctx->tx_buf);
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} else {
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txd = 0U;
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}
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while (!(litex_read8(dev_config->core_master_status_addr) &
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BIT(SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET))) {
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;
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}
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LOG_DBG("txd: 0x%x", txd);
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litex_write32(txd, dev_config->core_master_rxtx_addr);
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spi_context_update_tx(ctx, data->dfs, len / data->dfs);
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while (!(litex_read8(dev_config->core_master_status_addr) &
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BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
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;
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}
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rxd = litex_read32(dev_config->core_master_rxtx_addr);
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LOG_DBG("rxd: 0x%x", rxd);
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if (spi_context_rx_buf_on(ctx)) {
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litex_spi_rx_put(len, &rxd, ctx->rx_buf);
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}
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spi_context_update_rx(ctx, data->dfs, len / data->dfs);
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} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
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litex_write32(0, dev_config->core_master_cs_addr);
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spi_context_complete(ctx, dev, 0);
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return ret;
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}
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static int spi_litex_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_litex_data *data = dev->data;
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int ret = spi_config(dev, config);
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if (ret) {
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return ret;
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}
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, data->dfs);
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ret = spi_litex_xfer(dev, config);
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return ret;
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_litex_transceive_async(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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return -ENOTSUP;
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_litex_release(const struct device *dev, const struct spi_config *config)
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{
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return 0;
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}
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/* Device Instantiation */
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static const struct spi_driver_api spi_litex_api = {
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.transceive = spi_litex_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_litex_transceive_async,
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#endif /* CONFIG_SPI_ASYNC */
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.release = spi_litex_release,
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};
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#define SPI_INIT(n) \
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static struct spi_litex_data spi_litex_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_litex_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_litex_data_##n, ctx), \
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}; \
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static struct spi_litex_dev_config spi_litex_cfg_##n = { \
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.core_mmap_dummy_bits_addr = DT_INST_REG_ADDR_BY_NAME(n, core_mmap_dummy_bits), \
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.core_master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_cs), \
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.core_master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_phyconfig), \
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.core_master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_rxtx), \
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.core_master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, core_master_rxtx), \
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.core_master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_status), \
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.phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
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.phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0) \
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\
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}; \
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DEVICE_DT_INST_DEFINE(n, NULL, NULL, &spi_litex_data_##n, &spi_litex_cfg_##n, POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, &spi_litex_api);
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DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)

‎dts/bindings/spi/litex,spi-litespi.yaml‎

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description: LiteX SPI LiteSPI Controller
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compatible: "litex,spi-litespi"
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include: spi-controller.yaml
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properties:
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reg:
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required: true

‎dts/riscv/riscv32-litex-vexriscv.dtsi‎

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@@ -93,6 +93,30 @@
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@e000c000 {
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compatible = "litex,spi-litespi";
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reg = <0xe000c000 0x4>,
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<0xe000c004 0x4>,
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<0xe000c008 0x4>,
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<0xe000c00c 0x4>,
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<0xe000c010 0x4>,
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<0xe000c800 0x4>,
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<0x60000000 0x1000000>;
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reg-names = "core_mmap_dummy_bits",
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"core_master_cs",
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"core_master_phyconfig",
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"core_master_rxtx",
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"core_master_status",
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"phy_clk_divisor",
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"flash_mmap";
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#address-cells = <1>;
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#size-cells = <0>;
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spiflash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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};
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};
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timer0: timer@e0002800 {
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compatible = "litex,timer0";
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interrupt-parent = <&intc0>;

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