dts: nxp: add ewm for mcxnx4x and ke1xz

Add ewm peripheral for nxp mcxnx4x and ke1xz.
Attach xtal32k to ewm for frdm_mcxn947.

Signed-off-by: Yves Wang <[email protected]>

Author: yvesll

boards/nxp/frdm_mcxn947/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024  NXP
+ * Copyright 2024-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/init.h>
@@ -442,6 +442,12 @@ void board_early_init_hook(void)
 	CLOCK_EnableClock(kCLOCK_Sai1);
 #endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ewm0))
+	CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToWake);
+	CLOCK_AttachClk(kXTAL32K2_to_EWM0);
+	CLOCK_EnableClock(kCLOCK_Ewm0);
+#endif
+
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
 }

dts/arm/nxp/nxp_ke1xz.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -152,6 +152,14 @@
 			#io-channel-cells = <1>;
 		};
 
+		ewm0: ewm@40061000 {
+			compatible = "nxp,ewm";
+			reg = <0x40061000 0x6>;
+			status = "disabled";
+			interrupts = <28 0>;
+			clk-divider = <0x0>;
+		};
+
 		lpuart0: uart@4006a000 {
 			compatible = "nxp,lpuart";
 			reg = <0x4006a000 0x1000>;

dts/arm/nxp/nxp_mcxnx4x_common.dtsi

@@ -681,6 +681,14 @@
 		clk-divider = <1>;
 	};
 
+	ewm0: ewm@c0000 {
+		compatible = "nxp,ewm";
+		reg = <0xc0000 0x6>;
+		interrupts = <100 0>;
+		status = "disabled";
+		clk-divider = <0x0>;
+	};
+
 	flexpwm0: flexpwm@ce000 {
 		compatible = "nxp,flexpwm";
 		reg = <0xce000 0x1000>;

soc/nxp/kinetis/ke1xz/soc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  * Copyright (c) 2019-2021 Vestas Wind Systems A/S
  *
  * Based on NXP k6x soc.c, which is:
@@ -142,6 +142,9 @@ __weak void clk_init(void)
 	CLOCK_SetIpSrc(kCLOCK_Adc0,
 		       DT_CLOCKS_CELL(DT_NODELABEL(adc0), ip_source));
 #endif
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ewm0))
+	CLOCK_EnableClock(kCLOCK_Ewm0);
+#endif
 }
 
 void soc_early_init_hook(void)