Skip to content

Commit d8a42c5

Browse files
ycsinycsin
committed
irq: multilevel: compile 3rd level IRQ APIs only when enabled
This revert the idea of 3fa7d78 from #78845. The 3rd level IRQ APIs won't compile when CONFIG_3RD_LEVEL_INTERRUPT_BITS=0. Updated testcase accordingly. Signed-off-by: Yong Cong Sin <[email protected]> Signed-off-by: Yong Cong Sin <[email protected]> Signed-off-by: Yong Cong Sin <[email protected]>
1 parent 049b243 commit d8a42c5

File tree

3 files changed

+98
-25
lines changed

3 files changed

+98
-25
lines changed

‎include/zephyr/irq_multilevel.h‎

Lines changed: 42 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -32,15 +32,19 @@ typedef union _z_irq {
3232
uint32_t l1: CONFIG_1ST_LEVEL_INTERRUPT_BITS;
3333
/* Second level interrupt bits */
3434
uint32_t l2: CONFIG_2ND_LEVEL_INTERRUPT_BITS;
35+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
3536
/* Third level interrupt bits */
3637
uint32_t l3: CONFIG_3RD_LEVEL_INTERRUPT_BITS;
38+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
3739
} bits;
3840

41+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
3942
/* Third level IRQ's interrupt controller */
4043
struct {
4144
/* IRQ of the third level interrupt aggregator */
4245
uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS;
4346
} l3_intc;
47+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
4448

4549
/* Second level IRQ's interrupt controller */
4650
struct {
@@ -61,16 +65,20 @@ static inline uint32_t _z_l2_irq(_z_irq_t irq)
6165
return irq.bits.l2 - 1;
6266
}
6367

68+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
6469
static inline uint32_t _z_l3_irq(_z_irq_t irq)
6570
{
6671
return irq.bits.l3 - 1;
6772
}
73+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
6874

6975
static inline unsigned int _z_irq_get_level(_z_irq_t z_irq)
7076
{
77+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
7178
if (z_irq.bits.l3 != 0) {
7279
return 3;
7380
}
81+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
7482

7583
if (z_irq.bits.l2 != 0) {
7684
return 2;
@@ -142,7 +150,9 @@ static inline unsigned int irq_to_level_2(unsigned int irq)
142150
.bits = {
143151
.l1 = 0,
144152
.l2 = irq + 1,
153+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
145154
.l3 = 0,
155+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
146156
},
147157
};
148158

@@ -168,6 +178,7 @@ static inline unsigned int irq_parent_level_2(unsigned int irq)
168178
return _z_l1_irq(z_irq);
169179
}
170180

181+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
171182
/**
172183
* @brief Return the 3rd level interrupt number
173184
*
@@ -241,6 +252,7 @@ static inline unsigned int irq_parent_level_3(unsigned int irq)
241252

242253
return _z_l2_irq(z_irq);
243254
}
255+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
244256

245257
/**
246258
* @brief Return the interrupt number for a given level
@@ -256,11 +268,14 @@ static inline unsigned int irq_from_level(unsigned int irq, unsigned int level)
256268
return irq;
257269
} else if (level == 2) {
258270
return irq_from_level_2(irq);
259-
} else if (level == 3) {
271+
}
272+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
273+
else if (level == 3) {
260274
return irq_from_level_3(irq);
261275
}
276+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
262277

263-
/* level is higher than 3 */
278+
/* level is higher than what's supported */
264279
__ASSERT_NO_MSG(false);
265280
return irq;
266281
}
@@ -279,11 +294,14 @@ static inline unsigned int irq_to_level(unsigned int irq, unsigned int level)
279294
return irq;
280295
} else if (level == 2) {
281296
return irq_to_level_2(irq);
282-
} else if (level == 3) {
297+
}
298+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
299+
else if (level == 3) {
283300
return irq_to_level_3(irq);
284301
}
302+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
285303

286-
/* level is higher than 3 */
304+
/* level is higher than what's supported */
287305
__ASSERT_NO_MSG(false);
288306
return irq;
289307
}
@@ -303,11 +321,14 @@ static inline unsigned int irq_parent_level(unsigned int irq, unsigned int level
303321
return irq;
304322
} else if (level == 2) {
305323
return irq_parent_level_2(irq);
306-
} else if (level == 3) {
324+
}
325+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
326+
else if (level == 3) {
307327
return irq_parent_level_3(irq);
308328
}
329+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
309330

310-
/* level is higher than 3 */
331+
/* level is higher than what's supported */
311332
__ASSERT_NO_MSG(false);
312333
return irq;
313334
}
@@ -322,19 +343,24 @@ static inline unsigned int irq_parent_level(unsigned int irq, unsigned int level
322343
static inline unsigned int irq_get_intc_irq(unsigned int irq)
323344
{
324345
const unsigned int level = irq_get_level(irq);
325-
326-
__ASSERT_NO_MSG(level <= 3);
327346
_z_irq_t z_irq = {
328347
.irq = irq,
329348
};
330349

350+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
351+
__ASSERT_NO_MSG(level <= 3);
331352
if (level == 3) {
332353
return z_irq.l3_intc.irq;
333-
} else if (level == 2) {
354+
}
355+
#else
356+
__ASSERT_NO_MSG(level <= 2);
357+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
358+
359+
if (level == 2) {
334360
return z_irq.l2_intc.irq;
335-
} else {
336-
return irq;
337361
}
362+
363+
return irq;
338364
}
339365

340366
/**
@@ -351,8 +377,12 @@ static inline unsigned int irq_increment(unsigned int irq, unsigned int val)
351377
.irq = irq,
352378
};
353379

354-
if (z_irq.bits.l3 != 0) {
380+
if (false) {
381+
/* so that it evaluates the next condition */
382+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
383+
} else if (z_irq.bits.l3 != 0) {
355384
z_irq.bits.l3 += val;
385+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
356386
} else if (z_irq.bits.l2 != 0) {
357387
z_irq.bits.l2 += val;
358388
} else {

‎tests/kernel/interrupt/src/multilevel_irq.c‎

Lines changed: 48 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -12,18 +12,15 @@
1212
ZTEST(interrupt_feature, test_multi_level_api)
1313
{
1414
/* Zephyr multilevel-encoded IRQ */
15-
const uint32_t irqn_l3 = DT_IRQN(DT_NODELABEL(test_l3_irq));
1615
const uint32_t irqn_l2 = DT_IRQN(DT_NODELABEL(test_l2_irq));
1716
const uint32_t irqn_l1 = DT_IRQN(DT_NODELABEL(test_l1_irq));
1817
/* Raw IRQ specified in the devicetree */
19-
const uint32_t raw_l3 = DT_IRQ(DT_NODELABEL(test_l3_irq), irq);
2018
const uint32_t raw_l2 = DT_IRQ(DT_NODELABEL(test_l2_irq), irq);
2119
const uint32_t raw_l1 = DT_IRQ(DT_NODELABEL(test_l1_irq), irq);
2220

2321
/**
2422
* - irq_get_level()
2523
*/
26-
zassert_equal(3, irq_get_level(irqn_l3));
2724
zassert_equal(2, irq_get_level(irqn_l2));
2825
zassert_equal(1, irq_get_level(irqn_l1));
2926

@@ -32,13 +29,59 @@ ZTEST(interrupt_feature, test_multi_level_api)
3229
* - irq_to_level_2()
3330
* - irq_parent_level_2()
3431
*/
35-
zassert_equal(irq_from_level_2(irqn_l3), raw_l2);
3632
zassert_equal(irq_from_level_2(irqn_l2), raw_l2);
3733

3834
zassert_equal(irq_to_level_2(raw_l2) & irqn_l2, irq_to_level_2(raw_l2));
3935

4036
zassert_equal(irq_parent_level_2(irqn_l2), raw_l1);
4137

38+
/**
39+
* - irq_from_level()
40+
* - irq_to_level()
41+
* - irq_parent_level()
42+
*/
43+
zassert_equal(irq_from_level(irqn_l2, 2), raw_l2);
44+
45+
zassert_equal(irq_to_level(raw_l2, 2) & irqn_l2, irq_to_level(raw_l2, 2));
46+
47+
zassert_equal(irq_parent_level(irqn_l2, 2), raw_l1);
48+
49+
/**
50+
* - irq_get_intc_irq()
51+
*/
52+
zassert_equal(irq_get_intc_irq(irqn_l2), irqn_l1);
53+
zassert_equal(irq_get_intc_irq(irqn_l1), irqn_l1);
54+
55+
const uint32_t irqn_l2_inc = DT_IRQN(DT_NODELABEL(test_l2_irq_inc));
56+
const uint32_t irqn_l1_inc = DT_IRQN(DT_NODELABEL(test_l1_irq_inc));
57+
58+
/**
59+
* - irq_increment()
60+
*/
61+
zassert_equal(irq_increment(irqn_l1, 1), irqn_l1_inc);
62+
zassert_equal(irq_increment(irqn_l2, 2), irqn_l2_inc);
63+
}
64+
65+
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
66+
ZTEST(interrupt_feature, test_multi_level_api_l3)
67+
{
68+
/* Zephyr multilevel-encoded IRQ */
69+
const uint32_t irqn_l2 = DT_IRQN(DT_NODELABEL(test_l2_irq));
70+
const uint32_t irqn_l3 = DT_IRQN(DT_NODELABEL(test_l3_irq));
71+
/* Raw IRQ specified in the devicetree */
72+
const uint32_t raw_l2 = DT_IRQ(DT_NODELABEL(test_l2_irq), irq);
73+
const uint32_t raw_l3 = DT_IRQ(DT_NODELABEL(test_l3_irq), irq);
74+
75+
/**
76+
* - irq_get_level()
77+
*/
78+
zassert_equal(3, irq_get_level(irqn_l3));
79+
80+
/**
81+
* - irq_from_level_2()
82+
*/
83+
zassert_equal(irq_from_level_2(irqn_l3), raw_l2);
84+
4285
/**
4386
* - irq_from_level_3()
4487
* - irq_to_level_3()
@@ -56,32 +99,24 @@ ZTEST(interrupt_feature, test_multi_level_api)
5699
* - irq_parent_level()
57100
*/
58101
zassert_equal(irq_from_level(irqn_l3, 2), raw_l2);
59-
zassert_equal(irq_from_level(irqn_l2, 2), raw_l2);
60102
zassert_equal(irq_from_level(irqn_l3, 3), raw_l3);
61103

62-
zassert_equal(irq_to_level(raw_l2, 2) & irqn_l2, irq_to_level(raw_l2, 2));
63104
zassert_equal(irq_to_level(raw_l3, 3) & irqn_l3, irq_to_level(raw_l3, 3));
64105

65-
zassert_equal(irq_parent_level(irqn_l2, 2), raw_l1);
66106
zassert_equal(irq_parent_level(irqn_l3, 3), raw_l2);
67107

68108
/**
69109
* - irq_get_intc_irq()
70110
*/
71111
zassert_equal(irq_get_intc_irq(irqn_l3), irqn_l2);
72-
zassert_equal(irq_get_intc_irq(irqn_l2), irqn_l1);
73-
zassert_equal(irq_get_intc_irq(irqn_l1), irqn_l1);
74112

75113
const uint32_t irqn_l3_inc = DT_IRQN(DT_NODELABEL(test_l3_irq_inc));
76-
const uint32_t irqn_l2_inc = DT_IRQN(DT_NODELABEL(test_l2_irq_inc));
77-
const uint32_t irqn_l1_inc = DT_IRQN(DT_NODELABEL(test_l1_irq_inc));
78114

79115
/**
80116
* - irq_increment()
81117
*/
82-
zassert_equal(irq_increment(irqn_l1, 1), irqn_l1_inc);
83-
zassert_equal(irq_increment(irqn_l2, 2), irqn_l2_inc);
84118
zassert_equal(irq_increment(irqn_l3, 3), irqn_l3_inc);
85119
}
120+
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
86121

87122
ZTEST_SUITE(gen_isr_table_multilevel, NULL, NULL, NULL, NULL, NULL);

‎tests/kernel/interrupt/testcase.yaml‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,3 +85,11 @@ tests:
8585
- EXTRA_DTC_OVERLAY_FILE="multilevel_irq.overlay"
8686
extra_configs:
8787
- CONFIG_TEST_MULTILEVEL_IRQ=y
88+
arch.interrupt.multilevel_l3:
89+
filter: CONFIG_MULTI_LEVEL_INTERRUPTS
90+
extra_args:
91+
- EXTRA_DTC_OVERLAY_FILE="multilevel_irq.overlay"
92+
extra_configs:
93+
- CONFIG_TEST_MULTILEVEL_IRQ=y
94+
- CONFIG_3RD_LEVEL_INTERRUPTS=y
95+
- CONFIG_3RD_LEVEL_INTERRUPT_BITS=11

0 commit comments

Comments
 (0)