drivers: clock_control: add clock rate definitions for MIPI and LCDIF

Add clock rate definitions for MIPI and LCDIF peripherals, to enable
retrival of these peripheral clock rates at runtime.

Signed-off-by: Daniel DeGrasse <[email protected]>

Author: danieldegrasse

drivers/clock_control/clock_control_mcux_syscon.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-22, NXP
+ * Copyright (c) 2020-23, NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -154,6 +154,18 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(
 		*rate = CLOCK_GetI3cClkFreq();
 		break;
 #endif
+
+#if defined(CONFIG_MIPI_DSI_MCUX_2L)
+	case MCUX_MIPI_DSI_DPHY_CLK:
+		*rate = CLOCK_GetMipiDphyClkFreq();
+		break;
+	case MCUX_MIPI_DSI_ESC_CLK:
+		*rate = CLOCK_GetMipiDphyEscTxClkFreq();
+		break;
+	case MCUX_LCDIF_PIXEL_CLK:
+		*rate = CLOCK_GetDcPixelClkFreq();
+		break;
+#endif
 	}
 
 	return 0;

include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2022, NXP
+ * Copyright 2020-2023, NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -44,4 +44,9 @@
 
 #define MCUX_I3C_CLK			30
 
+#define MCUX_MIPI_DSI_DPHY_CLK		31
+#define MCUX_MIPI_DSI_ESC_CLK		32
+
+#define MCUX_LCDIF_PIXEL_CLK		33
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */