dts: renesas: Add ADC support for Renesas RZ/A3UL, T2M, N2L, V2L

Add ADC nodes to Renesas RZ/A3UL, T2M, N2L, V2L

Signed-off-by: Phuc Pham <[email protected]>
Signed-off-by: Tien Nguyen <[email protected]>

Author: Phuc Pham

dts/arm/renesas/rz/rzn/r9a07g084.dtsi

@@ -6,6 +6,7 @@
 #include <mem.h>
 #include <arm/armv8-r.dtsi>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 
 / {
 	#address-cells = <1>;
@@ -88,6 +89,30 @@
 			};
 		};
 
+		adc0: adc0@90004000 {
+			compatible = "renesas,rz-adc";
+			reg = <0x90004000 0x1000>;
+			unit = <0>;
+			interrupts = <GIC_SPI 345 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "scanend";
+			#io-channel-cells = <1>;
+			vref-mv = <1800>;
+			channel-available-mask = <0xF>;
+			status = "disabled";
+		};
+
+		adc1: adc1@80045000 {
+			compatible = "renesas,rz-adc";
+			reg = <0x80045000 0x1000>;
+			unit = <1>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "scanend";
+			#io-channel-cells = <1>;
+			vref-mv = <1800>;
+			channel-available-mask = <0xFF>;
+			status = "disabled";
+		};
+
 		icu: icu@81048000 {
 			reg = <0x81048000 0x1000>;
 			interrupt-parent = <&gic>;

dts/arm/renesas/rz/rzt/r9a07g075.dtsi

@@ -8,6 +8,7 @@
 #include <mem.h>
 #include <arm/armv8-r.dtsi>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 
 / {
 	compatible = "renesas,r9a07g075";
@@ -95,6 +96,30 @@
 			};
 		};
 
+		adc0: adc0@90004000 {
+			compatible = "renesas,rz-adc";
+			reg = <0x90004000 0x1000>;
+			unit = <0>;
+			interrupts = <GIC_SPI 345 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "scanend";
+			#io-channel-cells = <1>;
+			vref-mv = <1800>;
+			channel-available-mask = <0xFF>;
+			status = "disabled";
+		};
+
+		adc1: adc1@80045000 {
+			compatible = "renesas,rz-adc";
+			reg = <0x80045000 0x1000>;
+			unit = <1>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "scanend";
+			#io-channel-cells = <1>;
+			vref-mv = <1800>;
+			channel-available-mask = <0xFFFF>;
+			status = "disabled";
+		};
+
 		icu: icu@81048000 {
 			reg = <0x81048000 0x1000>;
 			interrupt-parent = <&gic>;

dts/arm/renesas/rz/rzv/r9a07g054.dtsi

@@ -6,6 +6,7 @@
 #include <arm/armv8-m.dtsi>
 #include <mem.h>
 #include <freq.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 
 / {
 	compatible = "renesas,r9a07g054";
@@ -32,6 +33,17 @@
 	};
 
 	soc {
+		adc: adc@40059000 {
+			compatible = "renesas,rz-adc-c";
+			reg = <0x40059000 DT_SIZE_K(1)>;
+			interrupts = <347 3>;
+			interrupt-names = "scanend";
+			#io-channel-cells = <1>;
+			vref-mv = <1800>;
+			channel-available-mask = <0xFF>;
+			status = "disabled";
+		};
+
 		pinctrl: pin-controller@41030000 {
 			compatible = "renesas,rzv-pinctrl";
 			reg = <0x41030000 DT_SIZE_K(64)>;

dts/arm64/renesas/rz/rza/r9a07g063.dtsi

@@ -9,6 +9,7 @@
 #include <arm64/armv8-a.dtsi>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 
 / {
 	compatible = "renesas,r9a07g063";
@@ -48,6 +49,17 @@
 			status = "okay";
 		};
 
+		adc: adc@10059000 {
+			compatible = "renesas,rz-adc-c";
+			reg = <0x10059000 DT_SIZE_K(1)>;
+			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "scanend";
+			#io-channel-cells = <1>;
+			vref-mv = <1800>;
+			channel-available-mask = <0x3>;
+			status = "disabled";
+		};
+
 		pinctrl: pin-controller@11030000 {
 			compatible = "renesas,rza-pinctrl";
 			reg = <0x11030000 DT_SIZE_K(64)>;