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| 1 | +/* |
| 2 | + * Copyright (c) 2025 Michal Piekos |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +/dts-v1/; |
| 8 | +#include <st/u5/stm32u585Xi.dtsi> |
| 9 | +#include <st/u5/stm32u585ciux-pinctrl.dtsi> |
| 10 | +#include <zephyr/dt-bindings/input/input-event-codes.h> |
| 11 | + |
| 12 | +/ { |
| 13 | + model = "WeAct Studio Black Pill STM32U585 Core Board"; |
| 14 | + compatible = "weact,blackpill-u585ci"; |
| 15 | + |
| 16 | + #address-cells = <1>; |
| 17 | + #size-cells = <1>; |
| 18 | + |
| 19 | + chosen { |
| 20 | + zephyr,console = &usart1; |
| 21 | + zephyr,shell-uart = &usart1; |
| 22 | + zephyr,sram = &sram0; |
| 23 | + zephyr,flash = &flash0; |
| 24 | + zephyr,canbus = &fdcan1; |
| 25 | + }; |
| 26 | + |
| 27 | + aliases { |
| 28 | + led0 = &led_0; |
| 29 | + sw0 = &button_0; |
| 30 | + watchdog0 = &iwdg; |
| 31 | + volt-sensor0 = &vref1; |
| 32 | + volt-sensor1 = &vbat4; |
| 33 | + die-temp0 = &die_temp; |
| 34 | + }; |
| 35 | + |
| 36 | + leds { |
| 37 | + compatible = "gpio-leds"; |
| 38 | + |
| 39 | + led_0: led0 { |
| 40 | + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; |
| 41 | + label = "User LED"; |
| 42 | + }; |
| 43 | + }; |
| 44 | + |
| 45 | + gpio_keys { |
| 46 | + compatible = "gpio-keys"; |
| 47 | + |
| 48 | + button_0: button0 { |
| 49 | + label = "User Button"; |
| 50 | + gpios = <&gpioa 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; |
| 51 | + zephyr,code = <INPUT_KEY_0>; |
| 52 | + }; |
| 53 | + }; |
| 54 | + |
| 55 | + zephyr,user { |
| 56 | + io-channels = <&adc1 16>, <&adc4 18>; |
| 57 | + }; |
| 58 | +}; |
| 59 | + |
| 60 | +&clk_hsi48 { |
| 61 | + status = "okay"; |
| 62 | +}; |
| 63 | + |
| 64 | +&clk_lse { |
| 65 | + status = "okay"; |
| 66 | +}; |
| 67 | + |
| 68 | +&clk_hse { |
| 69 | + clock-frequency = <DT_FREQ_M(25)>; |
| 70 | + status = "okay"; |
| 71 | +}; |
| 72 | + |
| 73 | +&clk_msis { |
| 74 | + status = "okay"; |
| 75 | + msi-range = <4>; |
| 76 | + msi-pll-mode; |
| 77 | +}; |
| 78 | + |
| 79 | +&pll1 { |
| 80 | + div-m = <5>; |
| 81 | + mul-n = <32>; |
| 82 | + div-q = <2>; |
| 83 | + div-r = <1>; |
| 84 | + clocks = <&clk_hse>; |
| 85 | + status = "okay"; |
| 86 | +}; |
| 87 | + |
| 88 | +&rcc { |
| 89 | + clocks = <&pll1>; |
| 90 | + clock-frequency = <DT_FREQ_M(160)>; |
| 91 | + ahb-prescaler = <1>; |
| 92 | + apb1-prescaler = <1>; |
| 93 | + apb2-prescaler = <1>; |
| 94 | + apb3-prescaler = <1>; |
| 95 | +}; |
| 96 | + |
| 97 | +&lpuart1 { |
| 98 | + pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>; |
| 99 | + pinctrl-names = "default"; |
| 100 | + current-speed = <115200>; |
| 101 | + status = "okay"; |
| 102 | +}; |
| 103 | + |
| 104 | +&usart1 { |
| 105 | + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; |
| 106 | + pinctrl-names = "default"; |
| 107 | + current-speed = <115200>; |
| 108 | + status = "okay"; |
| 109 | +}; |
| 110 | + |
| 111 | +&i2c1 { |
| 112 | + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb3>; |
| 113 | + pinctrl-names = "default"; |
| 114 | + status = "okay"; |
| 115 | + clock-frequency = <I2C_BITRATE_FAST>; |
| 116 | +}; |
| 117 | + |
| 118 | +&i2c2 { |
| 119 | + pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb14>; |
| 120 | + pinctrl-names = "default"; |
| 121 | + status = "okay"; |
| 122 | + clock-frequency = <I2C_BITRATE_FAST>; |
| 123 | +}; |
| 124 | + |
| 125 | +&spi1 { |
| 126 | + pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa1 |
| 127 | + &spi1_miso_pa6 &spi1_mosi_pa7>; |
| 128 | + pinctrl-names = "default"; |
| 129 | + status = "okay"; |
| 130 | +}; |
| 131 | + |
| 132 | +&fdcan1 { |
| 133 | + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>, |
| 134 | + <&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>; |
| 135 | + pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; |
| 136 | + pinctrl-names = "default"; |
| 137 | + status = "okay"; |
| 138 | +}; |
| 139 | + |
| 140 | +&adc1 { |
| 141 | + pinctrl-0 = <&adc1_in16_pb1>; |
| 142 | + pinctrl-names = "default"; |
| 143 | + st,adc-clock-source = "ASYNC"; |
| 144 | + st,adc-prescaler = <4>; |
| 145 | + status = "okay"; |
| 146 | +}; |
| 147 | + |
| 148 | +&adc4 { |
| 149 | + pinctrl-0 = <&adc4_in18_pb0>; |
| 150 | + pinctrl-names = "default"; |
| 151 | + st,adc-clock-source = "ASYNC"; |
| 152 | + st,adc-prescaler = <4>; |
| 153 | + status = "okay"; |
| 154 | +}; |
| 155 | + |
| 156 | +&dac1 { |
| 157 | + /* CAUTION: DAC on PA4 may conflict with SPI1 NSS on same pin */ |
| 158 | + pinctrl-0 = <&dac1_out1_pa4>; |
| 159 | + pinctrl-names = "default"; |
| 160 | + status = "disabled"; |
| 161 | +}; |
| 162 | + |
| 163 | +&timers3 { |
| 164 | + st,prescaler = <10000>; |
| 165 | + status = "okay"; |
| 166 | + |
| 167 | + pwm3: pwm { |
| 168 | + pinctrl-0 = <&tim3_ch1_pb4>; |
| 169 | + pinctrl-names = "default"; |
| 170 | + status = "okay"; |
| 171 | + }; |
| 172 | +}; |
| 173 | + |
| 174 | +&timers4 { |
| 175 | + st,prescaler = <10000>; |
| 176 | + status = "okay"; |
| 177 | + |
| 178 | + pwm4: pwm { |
| 179 | + pinctrl-0 = <&tim4_ch2_pb7>; |
| 180 | + pinctrl-names = "default"; |
| 181 | + status = "okay"; |
| 182 | + }; |
| 183 | +}; |
| 184 | + |
| 185 | +zephyr_udc0: &usbotg_fs { |
| 186 | + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; |
| 187 | + pinctrl-names = "default"; |
| 188 | + status = "okay"; |
| 189 | + |
| 190 | + cdc_acm_uart0: cdc_acm_uart0 { |
| 191 | + compatible = "zephyr,cdc-acm-uart"; |
| 192 | + }; |
| 193 | +}; |
| 194 | + |
| 195 | +&iwdg { |
| 196 | + status = "okay"; |
| 197 | +}; |
| 198 | + |
| 199 | +&rng { |
| 200 | + status = "okay"; |
| 201 | +}; |
| 202 | + |
| 203 | +&gpdma1 { |
| 204 | + status = "okay"; |
| 205 | +}; |
| 206 | + |
| 207 | +&die_temp { |
| 208 | + status = "okay"; |
| 209 | +}; |
| 210 | + |
| 211 | +&rtc { |
| 212 | + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>, |
| 213 | + <&rcc STM32_SRC_LSE RTC_SEL(1)>; |
| 214 | + status = "okay"; |
| 215 | +}; |
| 216 | + |
| 217 | +&vref1 { |
| 218 | + status = "okay"; |
| 219 | +}; |
| 220 | + |
| 221 | +&vbat4 { |
| 222 | + status = "okay"; |
| 223 | +}; |
| 224 | + |
| 225 | +&clk_lsi { |
| 226 | + status = "okay"; |
| 227 | +}; |
| 228 | + |
| 229 | +stm32_lp_tick_source: &lptim1 { |
| 230 | + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>, |
| 231 | + <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; |
| 232 | + status = "okay"; |
| 233 | +}; |
| 234 | + |
| 235 | +&backup_sram { |
| 236 | + status = "okay"; |
| 237 | +}; |
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