dts: nxp: Fix RT11xx DT files hierarchy

decsny · danieldegrasse · commit dba69f3f14e5 · 2025-06-27T18:27:26.000-05:00
The DT hierachy of the RT11xx series was somewhat incoherent. The boards
targets were directly including the series level DTSI with no SOC dtsi
in between, and there existed an SOC DTSI that had to be separately
included by a different board file, which didn't include the series DTSI
itself. It seems that this was only working if you included the files
exactly in the correct order in specific board files. Also, as a result
of this change, need to (correctly) define the cpu core only in the DTSI
for that core, instead of in the series generic dtsi, because that DTSI
was actually written with incorrect syntax due to duplicated node labels
on nodes right next to each other in the same file, and was relying on
other DTSI files to delete the duplicate nodes in order for it to build.
So overall this was a mess, needed cleanup.

Signed-off-by: Declan Snyder &lt;declan.snyder@nxp.com&gt;
diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_rt11xx_cm4.dtsi>
+#include <nxp/nxp_rt1160_cm4.dtsi>
 #include "mimxrt1160_evk.dtsi"
 
 / {
diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_rt11xx_cm7.dtsi>
+#include <nxp/nxp_rt1160_cm7.dtsi>
 #include "mimxrt1160_evk.dtsi"
 
 / {
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_rt11xx_cm4.dtsi>
+#include <nxp/nxp_rt1170_cm4.dtsi>
 #include "mimxrt1170_evk.dtsi"
 
 / {
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_rt11xx_cm7.dtsi>
+#include <nxp/nxp_rt1170_cm7.dtsi>
 #include "mimxrt1170_evk.dtsi"
 
 / {
diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_rt11xx_cm7.dtsi>
+#include <nxp/nxp_rt1170_cm7.dtsi>
 #include <zephyr/dt-bindings/led/led.h>
 #include "vmu_rt1170.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
diff --git a/dts/arm/nxp/nxp_rt1160.dtsi b/dts/arm/nxp/nxp_rt1160.dtsi
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <nxp/nxp_rt11xx.dtsi>
+
 /* Configure ARM PLL to 600MHz */
 &arm_pll {
 	clock-mult = <100>;
diff --git a/dts/arm/nxp/nxp_rt1160_cm4.dtsi b/dts/arm/nxp/nxp_rt1160_cm4.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SOC DTS for RT1160 cm4 core */
+
+/* Includes the series level for cm4 core, as opposed to cm7, shared with RT1170 */
+#include <nxp/nxp_rt11xx_cm4.dtsi>
+
+/* Includes the specifics for RT1170 SOC, as opposed to RT1170 */
+#include <nxp/nxp_rt1160.dtsi>
diff --git a/dts/arm/nxp/nxp_rt1160_cm7.dtsi b/dts/arm/nxp/nxp_rt1160_cm7.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SOC DTS for RT1160 cm7 core */
+
+/* Includes the series level for cm7 core, as opposed to cm4, shared with RT1170 */
+#include <nxp/nxp_rt11xx_cm7.dtsi>
+
+/* Includes the specifics for RT1170 SOC, as opposed to RT1170 */
+#include <nxp/nxp_rt1160.dtsi>
diff --git a/dts/arm/nxp/nxp_rt1170.dtsi b/dts/arm/nxp/nxp_rt1170.dtsi
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <nxp/nxp_rt11xx.dtsi>
+
 /* Configure ARM PLL to 996MHz */
 &arm_pll {
 	clock-mult = <83>;
diff --git a/dts/arm/nxp/nxp_rt1170_cm4.dtsi b/dts/arm/nxp/nxp_rt1170_cm4.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SOC DTS for RT1170 cm4 core */
+
+/* Includes the series level for cm4 core, as opposed to cm7, shared with RT1160 */
+#include <nxp/nxp_rt11xx_cm4.dtsi>
+
+/* Includes the specifics for RT1170 SOC, as opposed to RT1160 */
+#include <nxp/nxp_rt1170.dtsi>
diff --git a/dts/arm/nxp/nxp_rt1170_cm7.dtsi b/dts/arm/nxp/nxp_rt1170_cm7.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SOC DTS for RT1170 cm7 core */
+
+/* Includes the series level for cm7 core, as opposed to cm4, shared with RT1160 */
+#include <nxp/nxp_rt11xx_cm7.dtsi>
+
+/* Includes the specifics for RT1170 SOC, as opposed to RT1160 */
+#include <nxp/nxp_rt1170.dtsi>
diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi
@@ -14,43 +14,10 @@
 #include <zephyr/dt-bindings/power/imx_spc.h>
 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
 / {
-	chosen {
-		zephyr,entropy = &caam;
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-m7";
-			reg = <0>;
-
-			#address-cells = <1>;
-			#size-cells = <1>;
-			d-cache-line-size = <32>;
-
-			mpu: mpu@e000ed90 {
-				compatible = "arm,armv7m-mpu";
-				reg = <0xe000ed90 0x40>;
-			};
-		};
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-m4f";
-			reg = <1>;
-			d-cache-line-size = <32>;
-
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			mpu: mpu@e000ed90 {
-				compatible = "arm,armv7m-mpu";
-				reg = <0xe000ed90 0x40>;
-			};
-		};
-
 		power-states {
 			/*
 			 * Power states are managed with set points (see page 30-35 of RT1170
@@ -840,14 +807,6 @@
 			};
 		};
 
-		caam: caam@40440000 {
-			compatible = "nxp,imx-caam";
-			reg = <0x40440000 0x81000>;
-			interrupts = <69 0>, <70 0>, <71 0>,
-				     <72 0>,  <73 0>,  <74 0>;
-			status = "okay";
-		};
-
 		usb1: usbd@40430000 {
 			compatible = "nxp,ehci";
 			reg = <0x40430000 0x200>;
diff --git a/dts/arm/nxp/nxp_rt11xx_cm4.dtsi b/dts/arm/nxp/nxp_rt11xx_cm4.dtsi
@@ -8,7 +8,20 @@
 
 / {
 	cpus {
-		/delete-node/ cpu@0;
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <1>;
+			d-cache-line-size = <32>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
 	};
 
 	/*
@@ -566,8 +579,3 @@
 		<&iomuxc_gpio_ad_31_gpio9_io30>,
 		<&iomuxc_gpio_ad_32_gpio9_io31>;
 };
-
-/* CAAM currently does not work on M4 because of cache API issues */
-&caam {
-	status = "disabled";
-};
diff --git a/dts/arm/nxp/nxp_rt11xx_cm7.dtsi b/dts/arm/nxp/nxp_rt11xx_cm7.dtsi
@@ -8,9 +8,27 @@
 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
 
 / {
+	chosen {
+		zephyr,entropy = &caam;
+	};
+
 	cpus {
-		/delete-node/ cpu@1;
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m7";
+			reg = <0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			d-cache-line-size = <32>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
 	};
+
 	/*
 	 * ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
 	 * to the M7 core alone, hence this EDMA controller has been designated M7 only.
@@ -20,6 +38,14 @@
 	 * Refer to Chapter 3 of the Reference Manual
 	 */
 	soc {
+		caam: caam@40440000 {
+			compatible = "nxp,imx-caam";
+			reg = <0x40440000 0x81000>;
+			interrupts = <69 0>, <70 0>, <71 0>,
+				     <72 0>,  <73 0>,  <74 0>;
+			status = "okay";
+		};
+
 		/delete-node/ dma-controller@40c14000;
 
 		flexram: flexram@40028000 {
