tests: drivers: counter_basic_api: Enable lpit test for mimxrt1180_evk

Enable test for all channels on both cm33 and cm7 core.
This test covers following test cases:
- test_set_top_value_with_alarm
- test_valid_function_without_alarm
- test_set_top_value_without_alarm
Signed-off-by: Felix Wang <[email protected]>

Author: FelixWang47831

tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm33.conf

@@ -1,6 +1,7 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 CONFIG_COUNTER_MCUX_QTMR=y
+CONFIG_COUNTER_MCUX_LPIT=y

tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,3 +9,63 @@
 	primary-source = "kQTMR_ClockDivide_128";
 	mode = "kQTMR_PriSrcRiseEdge";
 };
+
+&lpit1 {
+	status = "okay";
+};
+
+&lpit1_channel0 {
+	status = "okay";
+};
+
+&lpit1_channel1 {
+	status = "okay";
+};
+
+&lpit1_channel2 {
+	status = "okay";
+};
+
+&lpit1_channel3 {
+	status = "okay";
+};
+
+&lpit2 {
+	status = "okay";
+};
+
+&lpit2_channel0 {
+	status = "okay";
+};
+
+&lpit2_channel1 {
+	status = "okay";
+};
+
+&lpit2_channel2 {
+	status = "okay";
+};
+
+&lpit2_channel3 {
+	status = "okay";
+};
+
+&lpit3 {
+	status = "okay";
+};
+
+&lpit3_channel0 {
+	status = "okay";
+};
+
+&lpit3_channel1 {
+	status = "okay";
+};
+
+&lpit3_channel2 {
+	status = "okay";
+};
+
+&lpit3_channel3 {
+	status = "okay";
+};

tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf

@@ -1,6 +1,7 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 CONFIG_COUNTER_MCUX_QTMR=y
+CONFIG_COUNTER_MCUX_LPIT=y

tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,3 +9,63 @@
 	primary-source = "kQTMR_ClockDivide_128";
 	mode = "kQTMR_PriSrcRiseEdge";
 };
+
+&lpit1 {
+	status = "okay";
+};
+
+&lpit1_channel0 {
+	status = "okay";
+};
+
+&lpit1_channel1 {
+	status = "okay";
+};
+
+&lpit1_channel2 {
+	status = "okay";
+};
+
+&lpit1_channel3 {
+	status = "okay";
+};
+
+&lpit2 {
+	status = "okay";
+};
+
+&lpit2_channel0 {
+	status = "okay";
+};
+
+&lpit2_channel1 {
+	status = "okay";
+};
+
+&lpit2_channel2 {
+	status = "okay";
+};
+
+&lpit2_channel3 {
+	status = "okay";
+};
+
+&lpit3 {
+	status = "okay";
+};
+
+&lpit3_channel0 {
+	status = "okay";
+};
+
+&lpit3_channel1 {
+	status = "okay";
+};
+
+&lpit3_channel2 {
+	status = "okay";
+};
+
+&lpit3_channel3 {
+	status = "okay";
+};

tests/drivers/counter/counter_basic_api/src/test_counter.c

@@ -123,6 +123,9 @@ static const struct device *const devices[] = {
 #ifdef CONFIG_COUNTER_MCUX_LPTMR
 	DEVS_FOR_DT_COMPAT(nxp_lptmr)
 #endif
+#ifdef CONFIG_COUNTER_MCUX_LPIT
+	DEVS_FOR_DT_COMPAT(nxp_lpit_channel)
+#endif
 #ifdef CONFIG_COUNTER_RENESAS_RZ_GTM
 	DEVS_FOR_DT_COMPAT(renesas_rz_gtm_counter)
 #endif