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drivers: mdio: Add Xilinx Axi Ethernet Lite driver
This commit adds support for the Xilinx AXI Ethernet Lite device, also known as the emaclite. The emaclite is a light-weight 10/100 MII Ethernet device. It can optionally be configured to include an MDIO. The MMIO interface is controlled via MMIO registers and requires the software to busy-wait until completion. Signed-off-by: Eric Ackermann <[email protected]>
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‎drivers/mdio/CMakeLists.txt‎

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@@ -20,4 +20,5 @@ zephyr_library_sources_ifdef(CONFIG_MDIO_RENESAS_RA mdio_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_LAN865X mdio_lan865x.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_SENSRY_SY1XX mdio_sy1xx.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_XILINX_AXI_ENET mdio_xilinx_axienet.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_XILINX_AXI_ETHERNET_LITE mdio_xilinx_axi_ethernet_lite.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_INTEL_IGC mdio_intel_igc.c)

‎drivers/mdio/Kconfig‎

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@@ -41,6 +41,7 @@ source "drivers/mdio/Kconfig.renesas_ra"
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source "drivers/mdio/Kconfig.lan865x"
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source "drivers/mdio/Kconfig.sy1xx"
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source "drivers/mdio/Kconfig.xilinx_axienet"
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source "drivers/mdio/Kconfig.xilinx_axi_ethernet_lite"
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source "drivers/mdio/Kconfig.intel_igc"
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config MDIO_INIT_PRIORITY

‎drivers/mdio/Kconfig.xilinx_axi_ethernet_lite‎

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# Copyright 2025 CISPA Helmholtz Center for Information Security
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# SPDX-License-Identifier: Apache-2.0
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config MDIO_XILINX_AXI_ETHERNET_LITE
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bool "Xilinx AXI Ethernet Lite MDIO driver"
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default y
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depends on DT_HAS_XLNX_XPS_ETHERNETLITE_3_00_A_MDIO_ENABLED
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depends on NETWORKING
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help
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Enable Xilinx AXI Ethernet Lite MDIO bus driver.

‎drivers/mdio/mdio_xilinx_axi_ethernet_lite.c‎

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/*
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* Xilinx AXI Ethernet Lite MDIO
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*
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* Copyright(c) 2025, CISPA Helmholtz Center for Information Security
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(eth_xilinx_axi_ethernet_lite_mdio, CONFIG_ETHERNET_LOG_LEVEL);
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/device.h>
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#include <stdint.h>
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MAX_PHY_DEVICES 32
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_OFFSET 0x07e4
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_WRITE_DATA_REG_OFFSET 0x07e8
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_READ_DATA_REG_OFFSET 0x07ec
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_OFFSET 0x07f0
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_MDIO_ENABLE_MASK BIT(3)
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_MDIO_BUSY_MASK BIT(0)
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_MDIO_DISABLE_MASK 0
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_OP_READ BIT(10)
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_OP_WRITE 0
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_SHIFT_REGADDR 0
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#define MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_SHIFT_PHYADDR 5
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struct mdio_xilinx_axi_ethernet_lite_data {
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struct k_mutex mutex;
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bool bus_enabled;
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};
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struct mdio_xilinx_axi_ethernet_lite_config {
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void *reg;
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};
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static inline uint32_t
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mdio_xilinx_axi_ethernet_lite_read_reg(const struct mdio_xilinx_axi_ethernet_lite_config *config,
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mem_addr_t reg)
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{
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return sys_read32((mem_addr_t)config->reg + reg);
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}
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static inline void
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mdio_xilinx_axi_ethernet_lite_write_reg(const struct mdio_xilinx_axi_ethernet_lite_config *config,
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mem_addr_t reg, uint32_t value)
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{
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sys_write32(value, (mem_addr_t)config->reg + reg);
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}
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static inline int
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mdio_xilinx_axi_ethernet_lite_check_busy(const struct mdio_xilinx_axi_ethernet_lite_config *config)
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{
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uint32_t mdio_control_reg_val = mdio_xilinx_axi_ethernet_lite_read_reg(
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config, MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_OFFSET);
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return mdio_control_reg_val & MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_MDIO_BUSY_MASK
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? -EBUSY
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: 0;
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}
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static inline void
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mdio_xilinx_axi_ethernet_lite_set_addr(const struct mdio_xilinx_axi_ethernet_lite_config *config,
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uint8_t prtad, uint8_t regad, bool is_read)
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{
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uint32_t mdio_addr_val = is_read ? MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_OP_READ
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: MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_OP_WRITE;
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/* range check done below in read/write functions */
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mdio_addr_val |= (uint32_t)regad
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<< MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_SHIFT_REGADDR;
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mdio_addr_val |= (uint32_t)prtad
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<< MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_SHIFT_PHYADDR;
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mdio_xilinx_axi_ethernet_lite_write_reg(
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config, MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_ADDRESS_REG_OFFSET, mdio_addr_val);
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}
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static inline void xilinx_axi_ethernet_lite_mdio_bus_enable(const struct device *dev)
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{
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const struct mdio_xilinx_axi_ethernet_lite_config *config = dev->config;
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struct mdio_xilinx_axi_ethernet_lite_data *data = dev->data;
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mdio_xilinx_axi_ethernet_lite_write_reg(
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config, MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_OFFSET,
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MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_MDIO_ENABLE_MASK);
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data->bus_enabled = true;
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}
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/* arbitrary but sufficient in testing */
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#define MDIO_MAX_WAIT_US 1000
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static inline int xilinx_axi_ethernet_lite_mdio_complete_transaction(
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const struct mdio_xilinx_axi_ethernet_lite_config *config)
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{
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int waited_cycles = 0;
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/* start transaction - everything set up */
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mdio_xilinx_axi_ethernet_lite_write_reg(
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config, MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_OFFSET,
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MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_MDIO_ENABLE_MASK |
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MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_CONTROL_REG_MDIO_BUSY_MASK);
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while (mdio_xilinx_axi_ethernet_lite_check_busy(config) &&
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waited_cycles < MDIO_MAX_WAIT_US) {
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/* no need to block the CPU */
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k_msleep(1);
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waited_cycles++;
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}
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if (waited_cycles == MDIO_MAX_WAIT_US) {
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LOG_ERR("Timed out waiting for MDIO transaction to complete!");
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return -EIO;
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}
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/* busy went low - transaction complete */
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return 0;
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}
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static int xilinx_axi_ethernet_lite_mdio_read(const struct device *dev, uint8_t prtad,
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uint8_t regad, uint16_t *value)
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{
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const struct mdio_xilinx_axi_ethernet_lite_config *config = dev->config;
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struct mdio_xilinx_axi_ethernet_lite_data *data = dev->data;
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if (prtad >= MDIO_XILINX_AXI_ETHERNET_LITE_MAX_PHY_DEVICES) {
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LOG_ERR("Requested read port address %" PRIu8 " not supported - max %d", prtad,
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MDIO_XILINX_AXI_ETHERNET_LITE_MAX_PHY_DEVICES);
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return -ENOSYS;
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}
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(void)k_mutex_lock(&data->mutex, K_FOREVER);
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if (!data->bus_enabled) {
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LOG_ERR("MDIO bus not enabled!");
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(void)k_mutex_unlock(&data->mutex);
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return -ENOSYS;
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}
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if (mdio_xilinx_axi_ethernet_lite_check_busy(config)) {
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LOG_ERR("MDIO bus busy!");
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(void)k_mutex_unlock(&data->mutex);
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return -ENOSYS;
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}
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mdio_xilinx_axi_ethernet_lite_set_addr(config, prtad, regad, true);
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if (xilinx_axi_ethernet_lite_mdio_complete_transaction(config)) {
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(void)k_mutex_unlock(&data->mutex);
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return -EIO;
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}
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*value = (uint16_t)mdio_xilinx_axi_ethernet_lite_read_reg(
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config, MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_READ_DATA_REG_OFFSET);
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(void)k_mutex_unlock(&data->mutex);
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return 0;
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}
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static int xilinx_axi_ethernet_lite_mdio_write(const struct device *dev, uint8_t prtad,
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uint8_t regad, uint16_t value)
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{
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const struct mdio_xilinx_axi_ethernet_lite_config *config = dev->config;
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struct mdio_xilinx_axi_ethernet_lite_data *data = dev->data;
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if (prtad >= MDIO_XILINX_AXI_ETHERNET_LITE_MAX_PHY_DEVICES) {
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LOG_ERR("Requested write port address %" PRIu8 " not supported - max %d", prtad,
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MDIO_XILINX_AXI_ETHERNET_LITE_MAX_PHY_DEVICES);
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return -ENOSYS;
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}
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(void)k_mutex_lock(&data->mutex, K_FOREVER);
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if (!data->bus_enabled) {
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LOG_ERR("MDIO bus not enabled!");
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(void)k_mutex_unlock(&data->mutex);
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return -ENOSYS;
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}
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if (mdio_xilinx_axi_ethernet_lite_check_busy(config)) {
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LOG_ERR("MDIO bus busy!");
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(void)k_mutex_unlock(&data->mutex);
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return -ENOSYS;
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}
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mdio_xilinx_axi_ethernet_lite_set_addr(config, prtad, regad, false);
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mdio_xilinx_axi_ethernet_lite_write_reg(
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config, MDIO_XILINX_AXI_ETHERNET_LITE_MDIO_WRITE_DATA_REG_OFFSET, value);
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if (xilinx_axi_ethernet_lite_mdio_complete_transaction(config)) {
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(void)k_mutex_unlock(&data->mutex);
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return -EIO;
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}
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(void)k_mutex_unlock(&data->mutex);
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return 0;
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}
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static int xilinx_axi_ethernet_lite_mdio_init(const struct device *dev)
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{
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struct mdio_xilinx_axi_ethernet_lite_data *data = dev->data;
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(void)k_mutex_init(&data->mutex);
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xilinx_axi_ethernet_lite_mdio_bus_enable(dev);
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return 0;
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}
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static DEVICE_API(mdio, mdio_xilinx_axi_ethernet_lite_api) = {
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/* clause 45 not supported */
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.read = xilinx_axi_ethernet_lite_mdio_read,
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.write = xilinx_axi_ethernet_lite_mdio_write};
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#define XILINX_AXI_ETHERNET_LITE_MDIO_INIT(inst) \
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\
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static const struct mdio_xilinx_axi_ethernet_lite_config \
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mdio_xilinx_axi_ethernet_lite_config##inst = { \
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.reg = (void *)(uintptr_t)DT_REG_ADDR(DT_INST_PARENT(inst)), \
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}; \
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static struct mdio_xilinx_axi_ethernet_lite_data \
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mdio_xilinx_axi_ethernet_lite_data##inst = {0}; \
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DEVICE_DT_INST_DEFINE(inst, xilinx_axi_ethernet_lite_mdio_init, NULL, \
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&mdio_xilinx_axi_ethernet_lite_data##inst, \
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&mdio_xilinx_axi_ethernet_lite_config##inst, POST_KERNEL, \
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CONFIG_MDIO_INIT_PRIORITY, &mdio_xilinx_axi_ethernet_lite_api);
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#define DT_DRV_COMPAT xlnx_xps_ethernetlite_3_00_a_mdio
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DT_INST_FOREACH_STATUS_OKAY(XILINX_AXI_ETHERNET_LITE_MDIO_INIT)

‎dts/bindings/mdio/xlnx,xps-ethernetlite-3.00.a-mdio.yaml‎

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# Copyright (c) 2025 CISPA Helmholtz Center for Information Security
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# SPDX-License-Identifier: Apache-2.0
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# Common fields for MDIO controllers
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include: mdio-controller.yaml
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compatible: xlnx,xps-ethernetlite-3.00.a-mdio
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description: MDIO interface of Xilinx AXI Ethernet Lite.

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