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drivers: gpio: bouffalolab: Add bflb gpio driver
Add Bouffalo Lab gpio driver. Signed-off-by: Camille BAUD <[email protected]> Signed-off-by: Gerson Fernando Budke <[email protected]>
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‎boards/bouffalolab/bl6/bl604e_iot_dvk/bl604e_iot_dvk.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ testing:
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- net
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- bluetooth
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supported:
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- gpio
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- pinctrl
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- uart
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vendor: bflb

‎boards/bouffalolab/bl6/bl604e_iot_dvk/doc/index.rst‎

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@@ -39,6 +39,8 @@ The board configuration supports the following hardware features:
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+===========+============+=======================+
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| MTIMER | on-chip | RISC-V Machine Timer |
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+-----------+------------+-----------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-----------------------+
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| PINCTRL | on-chip | pin muxing |
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+-----------+------------+-----------------------+
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| UART | on-chip | serial port-polling; |

‎drivers/gpio/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_AW9523B gpio_aw9523b.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AXP192 gpio_axp192.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BCM2711 gpio_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BD8LB600FS gpio_bd8lb600fs.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BFLB gpio_bflb.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BRCMSTB gpio_brcmstb.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CC13XX_CC26XX gpio_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX gpio_cc32xx.c)

‎drivers/gpio/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -105,6 +105,7 @@ source "drivers/gpio/Kconfig.axp192"
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source "drivers/gpio/Kconfig.b91"
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source "drivers/gpio/Kconfig.bcm2711"
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source "drivers/gpio/Kconfig.bd8lb600fs"
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source "drivers/gpio/Kconfig.bflb"
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source "drivers/gpio/Kconfig.brcmstb"
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source "drivers/gpio/Kconfig.cc13xx_cc26xx"
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source "drivers/gpio/Kconfig.cc32xx"

‎drivers/gpio/Kconfig.bflb‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
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# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_BFLB
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bool "Bouffalo Lab GPIO driver"
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depends on DT_HAS_BFLB_BL_GPIO_ENABLED
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default y
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help
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Bouffalo Lab GPIO driver

‎drivers/gpio/gpio_bflb.c‎

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@@ -0,0 +1,324 @@
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/*
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* Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT bflb_bl_gpio
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <bouffalolab/common/gpio_reg.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_bflb, CONFIG_GPIO_LOG_LEVEL);
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#define CLEAR_TIMEOUT_COUNTER 32
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/* clang-format off */
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struct gpio_bflb_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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uint32_t base_reg;
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void (*irq_config_func)(const struct device *dev);
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void (*irq_enable_func)(const struct device *dev);
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};
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struct gpio_bflb_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t callbacks;
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};
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static int gpio_bflb_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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*value = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL30_OFFSET);
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return 0;
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}
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static int gpio_bflb_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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uint32_t tmp = 0;
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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tmp = (tmp & ~mask) | (mask & value);
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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return 0;
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}
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static int gpio_bflb_port_set_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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uint32_t tmp = 0;
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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tmp |= mask;
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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return 0;
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}
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static int gpio_bflb_port_clear_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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uint32_t tmp = 0;
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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tmp &= ~mask;
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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return 0;
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}
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static int gpio_bflb_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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uint32_t tmp = 0;
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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tmp ^= mask;
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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return 0;
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}
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static void gpio_bflb_port_interrupt_configure_mode(const struct device *dev,
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uint32_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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uint32_t tmp = 0;
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uint8_t trig_mode = 0; /* default to 'sync' mode */
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 10) << 2));
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tmp &= ~(0x07 << ((pin % 10) * 3)); /* clear modes */
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if ((trig & GPIO_INT_HIGH_1) != 0) {
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trig_mode |= 1;
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}
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if (!(mode & GPIO_INT_EDGE)) {
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trig_mode |= 2;
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}
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tmp |= (trig_mode << ((pin % 10) * 3));
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 10) << 2));
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}
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static void gpio_bflb_pin_interrupt_clear(const struct device *dev, uint32_t mask)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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int32_t timeout = CLEAR_TIMEOUT_COUNTER;
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sys_write32(mask, cfg->base_reg + GLB_GPIO_INT_CLR1_OFFSET);
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while ((sys_read32(cfg->base_reg + GLB_GPIO_INT_STAT1_OFFSET) & mask) != 0
128+
&& timeout > 0) {
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--timeout;
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}
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sys_write32(0x0, cfg->base_reg + GLB_GPIO_INT_CLR1_OFFSET);
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}
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static int gpio_bflb_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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uint32_t tmp = 0;
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/* Disable the interrupt. */
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_INT_MASK1_OFFSET);
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tmp |= BIT(pin);
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_INT_MASK1_OFFSET);
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gpio_bflb_port_interrupt_configure_mode(dev, pin, mode, trig);
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if (mode != GPIO_INT_MODE_DISABLED) {
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/* clear */
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gpio_bflb_pin_interrupt_clear(dev, BIT(pin));
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/* unmask */
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_INT_MASK1_OFFSET);
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tmp &= ~BIT(pin);
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_INT_MASK1_OFFSET);
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} else {
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/* mask */
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_INT_MASK1_OFFSET);
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tmp |= BIT(pin);
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_INT_MASK1_OFFSET);
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}
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/* enable clic interrupt for us as it gets cleared in soc init */
166+
cfg->irq_enable_func(dev);
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return 0;
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}
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static int gpio_bflb_config(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags)
172+
{
173+
const struct gpio_bflb_config *const cfg = dev->config;
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uint8_t is_odd = 0;
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uint32_t cfg_address;
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uint32_t tmp = 0;
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uint32_t tmp_a = 0;
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uint32_t tmp_b = 0;
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/* Disable output anyway */
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tmp_a = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
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tmp_a &= ~(1 << (pin & 0x1f));
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sys_write32(tmp_a, cfg->base_reg + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
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185+
is_odd = pin & 1;
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cfg_address = cfg->base_reg + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4);
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tmp_b = sys_read32(cfg_address);
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tmp_a = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
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if ((flags & GPIO_INPUT) != 0) {
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tmp_b |= (1 << (is_odd * 16 + 0));
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tmp_a &= ~(1 << (pin & 0x1f));
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} else {
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tmp_b &= ~(1 << (is_odd * 16 + 0));
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}
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if ((flags & GPIO_OUTPUT) != 0) {
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tmp_a |= (1 << (pin & 0x1f));
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tmp_b &= ~(1 << (is_odd * 16 + 0));
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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tmp = tmp | pin;
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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tmp = tmp & ~pin;
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sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFGCTL32_OFFSET);
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}
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} else {
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tmp_a &= ~(1 << (pin & 0x1f));
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}
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sys_write32(tmp_a, cfg->base_reg + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
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if ((flags & GPIO_PULL_UP) != 0) {
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tmp_b |= (1 << (is_odd * 16 + 4));
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tmp_b &= ~(1 << (is_odd * 16 + 5));
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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tmp_b |= (1 << (is_odd * 16 + 5));
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tmp_b &= ~(1 << (is_odd * 16 + 4));
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} else {
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tmp_b &= ~(1 << (is_odd * 16 + 4));
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tmp_b &= ~(1 << (is_odd * 16 + 5));
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}
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/* GPIO mode */
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tmp_b &= ~(0x1f << (is_odd * 16 + 8));
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tmp_b |= (11 << (is_odd * 16 + 8));
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/* enabled SMT in GPIO mode */
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tmp_b |= (1 << (is_odd * 16 + 1));
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sys_write32(tmp_b, cfg_address);
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return 0;
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}
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static int gpio_bflb_init(const struct device *dev)
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{
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const struct gpio_bflb_config *const cfg = dev->config;
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/* nothing to do beside link irq */
247+
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cfg->irq_config_func(dev);
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return 0;
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}
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static void gpio_bflb_isr(const struct device *dev)
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{
255+
const struct gpio_bflb_config *const cfg = dev->config;
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struct gpio_bflb_data *data = dev->data;
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uint32_t int_stat;
258+
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/* interrupt data is in format 1 bit = 1 pin */
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int_stat = sys_read32(cfg->base_reg + GLB_GPIO_INT_STAT1_OFFSET);
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262+
gpio_fire_callbacks(&data->callbacks, dev, int_stat);
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/* clear interrupts */
265+
gpio_bflb_pin_interrupt_clear(dev, int_stat);
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}
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static int gpio_bflb_manage_callback(const struct device *port,
269+
struct gpio_callback *callback,
270+
bool set)
271+
{
272+
struct gpio_bflb_data *data = port->data;
273+
274+
return gpio_manage_callback(&(data->callbacks), callback, set);
275+
}
276+
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static const struct gpio_driver_api gpio_bflb_api = {
278+
.pin_configure = gpio_bflb_config,
279+
.port_get_raw = gpio_bflb_port_get_raw,
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.port_set_masked_raw = gpio_bflb_port_set_masked_raw,
281+
.port_set_bits_raw = gpio_bflb_port_set_bits_raw,
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.port_clear_bits_raw = gpio_bflb_port_clear_bits_raw,
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.port_toggle_bits = gpio_bflb_port_toggle_bits,
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.pin_interrupt_configure = gpio_bflb_pin_interrupt_configure,
285+
.manage_callback = gpio_bflb_manage_callback,
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};
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288+
#define GPIO_BFLB_INIT(n) \
289+
static void port_##n##_bflb_irq_config_func(const struct device *dev); \
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static void port_##n##_bflb_irq_enable_func(const struct device *dev); \
291+
\
292+
static const struct gpio_bflb_config port_##n##_bflb_config = { \
293+
.common = { \
294+
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
295+
}, \
296+
.base_reg = DT_INST_REG_ADDR(n), \
297+
.irq_config_func = port_##n##_bflb_irq_config_func, \
298+
.irq_enable_func = port_##n##_bflb_irq_enable_func, \
299+
}; \
300+
\
301+
static struct gpio_bflb_data port_##n##_bflb_data; \
302+
\
303+
DEVICE_DT_INST_DEFINE(n, gpio_bflb_init, NULL, \
304+
&port_##n##_bflb_data, \
305+
&port_##n##_bflb_config, PRE_KERNEL_1, \
306+
CONFIG_GPIO_INIT_PRIORITY, \
307+
&gpio_bflb_api); \
308+
\
309+
static void port_##n##_bflb_irq_config_func(const struct device *dev) \
310+
{ \
311+
IRQ_CONNECT(DT_INST_IRQN(n), \
312+
DT_INST_IRQ(n, priority), \
313+
gpio_bflb_isr, \
314+
DEVICE_DT_INST_GET(n), 0); \
315+
} \
316+
\
317+
static void port_##n##_bflb_irq_enable_func(const struct device *dev) \
318+
{ \
319+
irq_enable(DT_INST_IRQN(n)); \
320+
}
321+
322+
DT_INST_FOREACH_STATUS_OKAY(GPIO_BFLB_INIT)
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324+
/* clang-format on */

‎dts/bindings/gpio/bflb,bl-gpio.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -11,20 +11,20 @@ include:
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- name: gpio-controller.yaml
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1313
properties:
14-
reg:
15-
required: true
14+
reg:
15+
required: true
1616

17-
interrupts:
18-
required: true
17+
interrupts:
18+
required: true
1919

20-
"#gpio-cells":
21-
const: 2
20+
"#gpio-cells":
21+
const: 2
2222

23-
"#bflb,pin-cells":
24-
type: int
25-
required: true
26-
const: 2
27-
description: Number of items to expect in a bflb,pins specifier
23+
"#bflb,pin-cells":
24+
type: int
25+
required: true
26+
const: 2
27+
description: Number of items to expect in a bflb,pins specifier
2828

2929
gpio-cells:
3030
- pin

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