drivers: ethernet: Add Xilinx AXI Enet driver

The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs.
This patch adds a driver and device tree bindings for the Ethernet MAC
core and its MDIO controller.
The driver was tested on a RISC-V softcore in an FPGA design, with an
RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree
bindings match the device tree generated by Vitis hsi. Note that Vitis
generates one of the two included compatible strings depending on
version.

Signed-off-by: Eric Ackermann <[email protected]>

Author: WorldofJARcraft

drivers/ethernet/CMakeLists.txt

@@ -44,6 +44,7 @@ zephyr_library_sources_ifdef(CONFIG_ETH_RENESAS_RA	eth_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_LAN9250		eth_lan9250.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_SY1XX		eth_sensry_sy1xx_mac.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_NXP_ENET	eth_nxp_enet.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_XILINX_AXIENET	eth_xilinx_axienet.c)
 
 if(CONFIG_ETH_NXP_S32_NETC)
   zephyr_library_sources(eth_nxp_s32_netc.c)

drivers/ethernet/Kconfig

@@ -76,6 +76,7 @@ source "drivers/ethernet/Kconfig.xmc4xxx"
 source "drivers/ethernet/Kconfig.test"
 source "drivers/ethernet/Kconfig.lan9250"
 source "drivers/ethernet/Kconfig.sy1xx_mac"
+source "drivers/ethernet/Kconfig.xilinx_axienet"
 
 source "drivers/ethernet/eth_nxp_enet_qos/Kconfig"
 

drivers/ethernet/Kconfig.xilinx_axienet

@@ -0,0 +1,41 @@
+#
+#Xilinx AXI 1G / 2.5G Ethernet Subsystem
+#
+#Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+#SPDX-License-Identifier: Apache-2.0
+#
+
+config ETH_XILINX_AXIENET
+	bool "Xilinx AXI Ethernet Driver"
+	default y
+	depends on DT_HAS_XLNX_AXI_ETHERNET_1_00_A_ENABLED
+	depends on DMA_XILINX_AXI_DMA
+	help
+		Enable Xilinx 1G / 2.5G AXI Ethernet driver,
+		commonly found on FPGAs.
+
+config ETH_XILINX_AXIENET_BUFFER_NUM_TX
+	int "Number of buffers for concurrent transmission (TX)."
+	depends on ETH_XILINX_AXIENET
+	default DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX
+	range 2 DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX
+	help
+		Number of buffers for transmission allocated in the Xilinx AXI Ethernet driver.
+		This limits how many transmissions can be in-flight at the same time.
+		This cannot exceed the number of available TX buffers in the AXI DMA. However,
+		in scenarios with multiple AXI DMAs for different purposes in the system, it
+		may be desirable to reduce the number of concurrent transmissions to conserve
+		resources.
+
+config ETH_XILINX_AXIENET_BUFFER_NUM_RX
+	int "Number of buffers for concurrent reception (RX)."
+	depends on ETH_XILINX_AXIENET
+	default DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX
+	range 2 DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX
+	help
+		Number of buffers for reception allocated in the Xilinx AXI Ethernet driver.
+		This limits how many transmissions can be in-flight at the same time.
+		This cannot exceed the number of available RX buffers in the AXI DMA. However,
+		in scenarios with multiple AXI DMAs for different purposes in the system, it
+		may be desirable to reduce the number of concurrent transmissions to conserve
+		resources.