drivers: gpio: imx rt11xx: fix wrong gpio pull disable mask

nelarsen · aescolar · commit dcfc3e787254 · 2024-07-08T09:30:15.000+02:00
Fixes: #75390 A wrong bit mask (wrong: IOMUXC_SW_PAD_CTL_PAD_PUS_MASK = 0x8) was used. That bit mask is for PUE/PUS-type gpio registers, but this is the section for registers with alternative PULL (PDRV) type layout. Right bit mask: IOMUXC_SW_PAD_CTL_PAD_PULL_MASK Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c
@@ -124,7 +124,7 @@ static int mcux_igpio_configure(const struct device *dev,
 			}
 		} else {
 			/* Set pin to no pull */
-			reg |= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
+			reg |= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
 		}
 		/* PDRV/SNVS/LPSR reg have different ODE bits */
 		if (config->pin_muxes[cfg_idx].pdrv_mux) {

Original file line number	Diff line number	Diff line change
`@@ -124,7 +124,7 @@ static int mcux_igpio_configure(const struct device *dev,`
`124`	`124`	`}`
`125`	`125`	`} else {`
`126`	`126`	`/* Set pin to no pull */`
`127`		`- reg \|= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;`
	`127`	`+ reg \|= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;`
`128`	`128`	`}`
`129`	`129`	`/* PDRV/SNVS/LPSR reg have different ODE bits */`
`130`	`130`	`if (config->pin_muxes[cfg_idx].pdrv_mux) {`