@@ -103,6 +103,7 @@ struct plic_stats {
103103};
104104
105105struct plic_data {
106+ struct k_spinlock lock ;
106107
107108#ifdef CONFIG_PLIC_SHELL_IRQ_COUNT
108109 struct plic_stats stats ;
@@ -279,11 +280,13 @@ static void plic_irq_enable_set_state(uint32_t irq, bool enable)
279280 */
280281void riscv_plic_irq_enable (uint32_t irq )
281282{
282- uint32_t key = irq_lock ();
283+ const struct device * dev = get_plic_dev_from_irq (irq );
284+ struct plic_data * data = dev -> data ;
285+ k_spinlock_key_t key = k_spin_lock (& data -> lock );
283286
284287 plic_irq_enable_set_state (irq , true);
285288
286- irq_unlock ( key );
289+ k_spin_unlock ( & data -> lock , key );
287290}
288291
289292/**
@@ -298,11 +301,13 @@ void riscv_plic_irq_enable(uint32_t irq)
298301 */
299302void riscv_plic_irq_disable (uint32_t irq )
300303{
301- uint32_t key = irq_lock ();
304+ const struct device * dev = get_plic_dev_from_irq (irq );
305+ struct plic_data * data = dev -> data ;
306+ k_spinlock_key_t key = k_spin_lock (& data -> lock );
302307
303308 plic_irq_enable_set_state (irq , false);
304309
305- irq_unlock ( key );
310+ k_spin_unlock ( & data -> lock , key );
306311}
307312
308313/**
@@ -316,11 +321,12 @@ void riscv_plic_irq_disable(uint32_t irq)
316321int riscv_plic_irq_is_enabled (uint32_t irq )
317322{
318323 const struct device * dev = get_plic_dev_from_irq (irq );
324+ struct plic_data * data = dev -> data ;
319325 const uint32_t local_irq = irq_from_level_2 (irq );
320326 uint32_t bit_position = local_irq & PLIC_REG_MASK ;
321327 uint32_t en_value ;
322328 int is_enabled = IS_ENABLED (CONFIG_PLIC_IRQ_AFFINITY ) ? 0 : 1 ;
323- uint32_t key = irq_lock ( );
329+ k_spinlock_key_t key = k_spin_lock ( & data -> lock );
324330
325331 for (uint32_t cpu_num = 0 ; cpu_num < arch_num_cpus (); cpu_num ++ ) {
326332 mem_addr_t en_addr =
@@ -334,7 +340,7 @@ int riscv_plic_irq_is_enabled(uint32_t irq)
334340 }
335341 }
336342
337- irq_unlock ( key );
343+ k_spin_unlock ( & data -> lock , key );
338344
339345 return is_enabled ;
340346}
@@ -413,7 +419,7 @@ const struct device *riscv_plic_get_dev(void)
413419int riscv_plic_irq_set_affinity (uint32_t irq , uint32_t cpumask )
414420{
415421 const struct device * dev = get_plic_dev_from_irq (irq );
416- const struct plic_data * data = dev -> data ;
422+ struct plic_data * data = dev -> data ;
417423 __maybe_unused const struct plic_config * config = dev -> config ;
418424 const uint32_t local_irq = irq_from_level_2 (irq );
419425
@@ -427,7 +433,7 @@ int riscv_plic_irq_set_affinity(uint32_t irq, uint32_t cpumask)
427433 return - EINVAL ;
428434 }
429435
430- uint32_t key = irq_lock ( );
436+ k_spinlock_key_t key = k_spin_lock ( & data -> lock );
431437
432438 /* Updated irq_cpumask for next time setting plic enable register */
433439 data -> irq_cpumask [local_irq ] = (plic_cpumask_t )cpumask ;
@@ -437,7 +443,7 @@ int riscv_plic_irq_set_affinity(uint32_t irq, uint32_t cpumask)
437443 riscv_plic_irq_enable (irq );
438444 }
439445
440- irq_unlock ( key );
446+ k_spin_unlock ( & data -> lock , key );
441447
442448 return 0 ;
443449}
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