soc: atmel_sam0: Add SAME51

This adds supoprt for the Atmel SAME51 SoC.

The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.

Signed-off-by: Benjamin Valentin <[email protected]>

Author: benpicco

soc/arm/atmel_sam0/common/CMakeLists.txt

@@ -8,6 +8,7 @@ zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD21 soc_samd2x.c)
 zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR21 soc_samd2x.c)
 
 zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD51 soc_samd5x.c)
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME51 soc_samd5x.c)
 zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME54 soc_samd5x.c)
 
 zephyr_include_directories(.)

soc/arm/atmel_sam0/same51/Kconfig.defconfig.series

@@ -0,0 +1,28 @@
+# Kconfig - Atmel SAME51 MCU series configuration options
+#
+# Copyright (c) 2019 ML!PA Consulting GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SAME51
+
+config SOC_SERIES
+	string
+	default "same51"
+
+config SOC_PART_NUMBER
+	string
+	default "same51j18a" if SOC_PART_NUMBER_SAME51J18A
+	default "same51j19a" if SOC_PART_NUMBER_SAME51J19A
+	default "same51j20a" if SOC_PART_NUMBER_SAME51J20A
+	default "same51n19a" if SOC_PART_NUMBER_SAME51N19A
+	default "same51n20a" if SOC_PART_NUMBER_SAME51N20A
+
+config NUM_IRQS
+	int
+	default 137
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 120000000
+
+endif # SOC_SERIES_SAME51

soc/arm/atmel_sam0/same51/Kconfig.series

@@ -0,0 +1,14 @@
+# Kconfig - Atmel SAME51 MCU series
+#
+# Copyright (c) 2019 ML!PA Consulting GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SAME51
+	bool "Atmel SAME51 MCU"
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_SAM0
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select ASF
+	help
+	  Enable support for Atmel SAME51 Cortex-M4F microcontrollers.

soc/arm/atmel_sam0/same51/Kconfig.soc

@@ -0,0 +1,25 @@
+# Kconfig - Atmel SAME51 MCU series
+#
+# Copyright (c) 2019 ML!PA Consulting GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+prompt "Atmel SAME51 MCU Selection"
+depends on SOC_SERIES_SAME51
+
+config SOC_PART_NUMBER_SAME51J18A
+	bool "SAME51J18A"
+
+config SOC_PART_NUMBER_SAME51J19A
+	bool "SAME51J19A"
+
+config SOC_PART_NUMBER_SAME51J20A
+	bool "SAME51J20A"
+
+config SOC_PART_NUMBER_SAME51N19A
+	bool "SAME51N19A"
+
+config SOC_PART_NUMBER_SAME51N20A
+	bool "SAME51N20A"
+
+endchoice

soc/arm/atmel_sam0/same51/dts_fixup.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2019 ML!PA Consulting GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define DT_FLASH_DEV_NAME DT_ATMEL_SAM0_NVMCTRL_0_LABEL
+
+#define CONFIG_ENTROPY_NAME DT_ATMEL_SAM0_TRNG_0_LABEL
+
+#define DT_NUM_IRQ_PRIO_BITS	DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+/* End of SoC Level DTS fixup file */

soc/arm/atmel_sam0/same51/linker.ld

@@ -0,0 +1,8 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2017 Google LLC.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/atmel_sam0/same51/soc.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019 ML!PA Consulting GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ATMEL_SAME51_SOC_H_
+#define _ATMEL_SAME51_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#define DONT_USE_CMSIS_INIT
+
+#include <zephyr/types.h>
+
+#if defined(CONFIG_SOC_PART_NUMBER_SAME51J18A)
+#include <same51j18a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAME51J19A)
+#include <same51j19a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAME51J20A)
+#include <same51j20a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAME51N19A)
+#include <same51n19a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAME51N20A)
+#include <same51n20a.h>
+#else
+#error Library does not support the specified device.
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#include "sercom_fixup_samd5x.h"
+#include "tc_fixup_samd5x.h"
+
+#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
+
+/** Processor Clock (HCLK) Frequency */
+#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
+/** Master Clock (MCK) Frequency */
+#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
+#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
+#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000
+
+#endif /* _ATMEL_SAME51_SOC_H_ */