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soc: ite: it82xx2: add it82000.bw variant support
as title. Signed-off-by: Ren Chen <[email protected]>
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‎dts/riscv/ite/it82000-pinctrl-map.dts‎

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/*
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* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
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#include <ite/it8xxx2-pinctrl-map.dtsi>
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&pinctrl {
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/* UART alternate function */
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/delete-node/ uart1_rx_gpb0_default;
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/delete-node/ uart1_tx_gpb1_default;
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/omit-if-no-ref/ uart1_rx_gpc7_default: uart1_rx_gpc7_default {
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pinmuxs = <&pinctrlc 7 IT8XXX2_ALT_FUNC_5>;
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};
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/omit-if-no-ref/ uart1_tx_gpe6_default: uart1_tx_gpe6_default {
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pinmuxs = <&pinctrle 6 IT8XXX2_ALT_FUNC_3>;
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};
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/* I2C alternate function */
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/delete-node/ i2c0_clk_gpb3_default;
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/delete-node/ i2c0_data_gpb4_default;
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/omit-if-no-ref/ i2c0_clk_gpf2_default: i2c0_clk_gpf2_default {
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pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_FUNC_1>;
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};
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/omit-if-no-ref/ i2c0_data_gpf3_default: i2c0_data_gpf3_default {
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pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_FUNC_1>;
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};
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};

‎dts/riscv/ite/it82000.dtsi‎

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/*
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* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/dt-util.h>
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#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
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#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
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#include <ite/it82xx2.dtsi>
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/ {
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soc {
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gpioq: gpio@f01611 {
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compatible = "ite,it8xxx2-gpio-v2";
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reg = <0x00f01611 1 /* GPDR (set) */
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0x00f01628 1 /* GPDMR (get) */
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0x00f01640 1 /* GPOTR */
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NO_FUNC 1 /* P18SCR */
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0x00f016e0 8>; /* GPCR */
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ngpios = <5>;
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gpio-reserved-ranges = <3 1>;
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gpio-controller;
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interrupts = <IT8XXX2_IRQ_WU184 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU185 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU186 IRQ_TYPE_LEVEL_HIGH
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NO_FUNC 0
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IT8XXX2_IRQ_WU188 IRQ_TYPE_LEVEL_HIGH
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NO_FUNC 0
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NO_FUNC 0
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NO_FUNC 0>;
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interrupt-parent = <&intc>;
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wuc-base = <0xf01b50 0xf01b50 0xf01b50 NO_FUNC 0xf01b50
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NO_FUNC NO_FUNC NO_FUNC>;
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wuc-mask = <BIT(0) BIT(1) BIT(2) 0 BIT(4) 0 0 0>;
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has-volt-sel = <0 0 0 0 0 0 0 0>;
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#gpio-cells = <2>;
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};
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};
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};
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&pinctrlb {
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func3-gcr = <NO_FUNC NO_FUNC 0xf03e11 NO_FUNC NO_FUNC 0xf03e11 NO_FUNC NO_FUNC>;
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func3-en-mask = <0 0 BIT(5) 0 0 BIT(5) 0 0>;
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func3-ext = <NO_FUNC NO_FUNC 0xf03e16 NO_FUNC NO_FUNC 0xf03e16 NO_FUNC NO_FUNC>;
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func3-ext-mask = <0 0 BIT(6) 0 0 BIT(6) 0 0>;
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volt-sel =<NO_FUNC NO_FUNC 0xf01649 NO_FUNC NO_FUNC 0xf01649 0xf01649 NO_FUNC>;
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volt-sel-mask = <0 0 BIT(2) 0 0 BIT(5) BIT(6) 0>;
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};
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&gpiob {
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ngpios = <7>;
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gpio-reserved-ranges = <0 2>, <3 2>;
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interrupts = <NO_FUNC 0
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NO_FUNC 0
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IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH
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NO_FUNC 0
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NO_FUNC 0
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IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH
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NO_FUNC 0>;
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wuc-base = <NO_FUNC NO_FUNC 0xf01b1c NO_FUNC NO_FUNC 0xf01b28 0xf01b28 NO_FUNC>;
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wuc-mask = <0 0 BIT(4) 0 0 BIT(0) BIT(1) 0>;
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has-volt-sel = <0 0 1 0 0 1 1 0>;
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};
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&pinctrlc {
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func5-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC NO_FUNC NO_FUNC NO_FUNC 0xf03e15>;
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func5-en-mask = <0 0 0 0 0 0 0 BIT(0)>;
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};
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&pinctrle {
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func3-gcr = <NO_FUNC 0xf03e16 0xf03e16 NO_FUNC NO_FUNC 0xf03e10 0xf03e15 NO_FUNC>;
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func3-en-mask = <0 BIT(5) BIT(5) 0 0 BIT(3) BIT(1) 0>;
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};
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&pinctrlf {
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func3-gcr = <0xf03e15 0xf03e15 NO_FUNC NO_FUNC NO_FUNC NO_FUNC 0xf03e11 NO_FUNC>;
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func3-en-mask = <BIT(2) BIT(3) 0 0 0 0 BIT(4) 0>;
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};
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&pinctrlg {
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func3-gcr = <0xf03e10 NO_FUNC 0xf03e10 NO_FUNC NO_FUNC NO_FUNC 0xf03e10 NO_FUNC>;
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func3-en-mask = <BIT(5) 0 BIT(4) 0 0 0 BIT(1) 0>;
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volt-sel = <0xf0164e NO_FUNC 0xf0164e NO_FUNC NO_FUNC NO_FUNC 0xf0164e NO_FUNC>;
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volt-sel-mask = <BIT(0) 0 BIT(2) 0 0 0 BIT(6) 0>;
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};
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&gpiog {
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ngpios = <8>;
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gpio-reserved-ranges = <1 1>;
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interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH
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NO_FUNC 0
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IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>;
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wuc-base = <0xf01b2c NO_FUNC 0xf01b2c 0xf01b30 0xf01b30 0xf01b30 0xf01b2c 0xf01b30>;
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wuc-mask = <BIT(3) 0 BIT(5) BIT(3) BIT(4) BIT(5) BIT(6) BIT(6)>;
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has-volt-sel = <1 0 1 0 0 0 1 0>;
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};

‎include/zephyr/dt-bindings/interrupt-controller/ite-intc.h‎

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@@ -172,6 +172,11 @@
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/* Group 23 */
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#define IT8XXX2_IRQ_WU149 184
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#define IT8XXX2_IRQ_WU150 185
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/* Group 27 */
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#define IT8XXX2_IRQ_WU184 216
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#define IT8XXX2_IRQ_WU185 217
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#define IT8XXX2_IRQ_WU186 218
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#define IT8XXX2_IRQ_WU188 220
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#define IT8XXX2_IRQ_COUNT (CONFIG_NUM_IRQS + 1)
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‎soc/ite/ec/it8xxx2/Kconfig‎

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@@ -47,6 +47,12 @@ config SOC_IT8XXX2_USBPD_PHY_V2
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This option is automatically selected by variant soc and sets
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the USBPD PHY version.
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config SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
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bool
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help
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This option indicates GPIO-Q group support and is
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automatically selected based on the SoC variant.
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config SOC_IT81302BX
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select SOC_IT8XXX2_REG_SET_V1
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select SOC_IT8XXX2_USBPD_PHY_V1
@@ -101,6 +107,11 @@ config SOC_IT82302BW
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT82000BW
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select SOC_IT8XXX2_REG_SET_V2
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
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config SOC_IT8XXX2_PLL_FLASH_48M
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bool "Flash frequency is 48MHz"
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default y

‎soc/ite/ec/it8xxx2/Kconfig.defconfig.it82000bw‎

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# Copyright (c) 2025 ITE Corporation.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_IT82000BW
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config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
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default y
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endif #SOC_IT82000BW

‎soc/ite/ec/it8xxx2/Kconfig.defconfig.series‎

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@@ -28,6 +28,7 @@ config VCMP_IT8XXX2_INIT_PRIORITY
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default 91 if VCMP_IT8XXX2_WORKQUEUE
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config NUM_IRQS
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default 221 if SOC_IT82000BW
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default 185
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config DYNAMIC_INTERRUPTS

‎soc/ite/ec/it8xxx2/Kconfig.soc‎

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@@ -59,6 +59,10 @@ config SOC_IT82302BW
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bool
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select SOC_IT8XXX2
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config SOC_IT82000BW
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bool
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select SOC_IT8XXX2
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config SOC_SERIES
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default "it8xxx2" if SOC_SERIES_IT8XXX2
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@@ -69,6 +73,7 @@ config SOC
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default "it81302bx" if SOC_IT81302BX
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default "it81302cx" if SOC_IT81302CX
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default "it81302dx" if SOC_IT81302DX
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default "it82000bw" if SOC_IT82000BW
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default "it82002aw" if SOC_IT82002AW
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default "it82002bw" if SOC_IT82002BW
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default "it82202ax" if SOC_IT82202AX

‎soc/ite/ec/it8xxx2/soc.c‎

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@@ -52,6 +52,12 @@ COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
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#define CLK_DIV_HIGH_FIELDS(n) FIELD_PREP(GENMASK(7, 4), n)
5353
#define CLK_DIV_LOW_FIELDS(n) FIELD_PREP(GENMASK(3, 0), n)
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#ifdef CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
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#define ELPM_BASE_ADDR 0xF03E00
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#define ELPMF5_INPUT_EN 0xF5
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#define XLPIN_INPUT_ENABLE_MASK GENMASK(5, 0)
59+
#endif /* CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED */
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5561
uint32_t chip_get_pll_freq(void)
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{
5763
uint32_t pllfreq;
@@ -527,6 +533,12 @@ static int ite_it8xxx2_init(void)
527533
}
528534
#endif /* (SOC_USBPD_ITE_PHY_PORT_COUNT > 0) */
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536+
#ifdef CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
537+
/* set gpio-q group as gpio by default */
538+
sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF5_INPUT_EN) & ~XLPIN_INPUT_ENABLE_MASK,
539+
ELPM_BASE_ADDR + ELPMF5_INPUT_EN);
540+
#endif /* CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED */
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530542
return 0;
531543
}
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SYS_INIT(ite_it8xxx2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

‎soc/ite/ec/soc.yml‎

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@@ -9,6 +9,7 @@ family:
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- name: it81302bx
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- name: it81302cx
1111
- name: it81302dx
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- name: it82000bw
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- name: it82002aw
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- name: it82002bw
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- name: it82202ax

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