spi: lpspi: rtio: Re-introduce native RTIO support

This version is based on the CPU LPSPI driver, directly implementing
the submit call following the non-blocking asynchronous pattern.

This has been re-introduced after struggling to keep up with data
streaming applications, which demands reduced and controlled latency,
which for the default implementation (using RTIO workqueue) is not
guaranteed, due to being serviced by a thread-pool vs directly in the
ISR context.

This version includes limited feature-set, yet stress-tested:
- Required both rx-fifo and tx-fifo to be equal.
- 8-byte words supported only.
- SPI Controller-only supported (target mode not included).
- SPI_HOLD_ON_CS only supported with CS GPIOs.

Signed-off-by: Luis Ubieda <[email protected]>

Author: ubieda

drivers/spi/spi_nxp_lpspi/CMakeLists.txt

@@ -2,4 +2,5 @@
 
 zephyr_library_sources_ifdef(CONFIG_SPI_NXP_LPSPI spi_nxp_lpspi_common.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_NXP_LPSPI_CPU spi_nxp_lpspi.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_NXP_LPSPI_CPU_RTIO spi_nxp_lpspi_rtio.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_NXP_LPSPI_DMA spi_nxp_lpspi_dma.c)

drivers/spi/spi_nxp_lpspi/Kconfig

@@ -31,11 +31,23 @@ config SPI_NXP_LPSPI_CPU
 	bool "NXP LPSPI CPU-based driver"
 	default y
 	depends on $(dt_compat_any_not_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas) || !SPI_NXP_LPSPI_DMA
+	depends on !SPI_NXP_LPSPI_CPU_RTIO
 	help
 	  Enable "normal" CPU based SPI driver for LPSPI.
 	  This has lower latency than DMA-based driver but over the
 	  longer transfers will likely have less bandwidth and use more CPU time.
 
+config SPI_NXP_LPSPI_CPU_RTIO
+	bool "NXP LPSPI RTIO-based driver"
+	default y
+	depends on $(dt_compat_any_not_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas) || !SPI_NXP_LPSPI_DMA
+	depends on SPI_RTIO
+	help
+	  Enable native RTIO-based driver for LPSPI.
+	  This driver optimizes latency by starting/resuming transfers directly
+	  from the ISR context in a non-blocking and asynchronous fashion. However,
+	  it does not include DMA usage.
+
 config SPI_NXP_LPSPI_TXFIFO_WAIT_CYCLES
 	int "Number of CPU cycles to wait on TX fifo empty"
 	default 0 if DEBUG
@@ -49,4 +61,19 @@ config SPI_NXP_LPSPI_TXFIFO_WAIT_CYCLES
 	  for if there is some programming error that causes TX fifo not to empty.
 	  The default of 10000 is arbitrary.
 
+if SPI_NXP_LPSPI_CPU_RTIO
+
+config SPI_NXP_RTIO_SQ_SIZE
+	int "Number of available submission queue entries"
+	default 8 # Sensible default that covers most common spi transactions
+	help
+	  When RTIO is use with SPI each driver holds a context with which blocking
+	  API calls use to perform SPI transactions. This queue needs to be as deep
+	  as the longest set of spi_buf_sets used, where normal SPI operations are
+	  used (equal length buffers). It may need to be slightly deeper where the
+	  spi buffer sets for transmit/receive are not always matched equally in
+	  length as these are transformed into normal transceives.
+
+endif # SPI_NXP_LPSPI_CPU_RTIO
+
 endif # SPI_NXP_LPSPI