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ragurram26nashif
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drivers: wifi: siwx91x: To improve SiWx91x performance
To enhance throughput performance on the SiWx91x series, Added some Siwx91x configurations by deafult. Signed-off-by: Rahul Gurram <[email protected]>
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dts/arm/silabs/siwg917.dtsi

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@
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* Less memory is allocated to Zephyr, more memory is allocated
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* to NWP, better are the WiFi and BLE performances.
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*/
67-
reg = <0x00000400 DT_SIZE_K(255)>;
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reg = <0x00000400 DT_SIZE_K(319)>;
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};
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7070
sram_dma1: memory-dma@24061c00 {
@@ -85,6 +85,7 @@
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support-1p8v;
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enable-xtal-correction;
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qspi-80mhz-clk;
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clock-frequency = <120000000>;
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status = "okay";
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bt_hci0: bt_hci {

dts/bindings/net/wireless/silabs,siwx91x-nwp.yaml

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Original file line numberDiff line numberDiff line change
@@ -77,3 +77,15 @@ properties:
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- "ext-gpios"
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- "internal"
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required: true
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clock-frequency:
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type: int
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enum:
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- 80000000
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- 120000000
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- 160000000
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required: true
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description: |
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SoC clock frequency configuration for the NWP in Hz. 80 MHz (80000000)
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is the default and offers lower power consumption; 120 MHz (120000000)
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can be used for higher throughput. 160 MHz (160000000) is not
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recommended due to potential instabilities

soc/silabs/silabs_siwx91x/siwg917/siwx91x_nwp.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ struct siwx91x_nwp_config {
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bool support_1p8v;
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bool enable_xtal_correction;
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bool qspi_80mhz_clk;
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uint32_t clock_frequency;
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};
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5354
typedef struct {
@@ -340,6 +341,7 @@ static int siwx91x_get_nwp_config(const struct device *dev,
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sl_wifi_device_configuration_t *get_config,
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uint8_t wifi_oper_mode, bool hidden_ssid, uint8_t max_num_sta)
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{
344+
const struct siwx91x_nwp_config *config = dev->config;
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sl_wifi_device_configuration_t default_config = {
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.region_code = siwx91x_map_country_code_to_region(DEFAULT_COUNTRY_CODE),
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.band = SL_SI91X_WIFI_BAND_2_4GHZ,
@@ -350,6 +352,11 @@ static int siwx91x_get_nwp_config(const struct device *dev,
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.custom_feature_bit_map = SL_SI91X_CUSTOM_FEAT_EXTENSION_VALID |
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SL_SI91X_CUSTOM_FEAT_ASYNC_CONNECTION_STATUS,
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.ext_custom_feature_bit_map = SL_SI91X_EXT_FEAT_XTAL_CLK,
355+
},
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.ta_pool = {
357+
.tx_ratio_in_buffer_pool = 1,
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.rx_ratio_in_buffer_pool = 1,
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.global_ratio_in_buffer_pool = 1
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}
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};
355362

@@ -371,6 +378,22 @@ static int siwx91x_get_nwp_config(const struct device *dev,
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siwx91x_apply_sram_config(boot_config);
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siwx91x_apply_boot_config(dev, boot_config);
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381+
/* Apply TA clock configuration based on DT property */
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switch (config->clock_frequency) {
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case 80000000:
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/* no configuration bit needed */
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break;
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case 120000000:
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boot_config->custom_feature_bit_map |= SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_120MHZ;
388+
break;
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case 160000000:
390+
boot_config->custom_feature_bit_map |= SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_160MHZ;
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break;
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default:
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__ASSERT(0, "Corrupted DT configuration");
394+
break;
395+
}
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switch (wifi_oper_mode) {
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case WIFI_STA_MODE:
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siwx91x_configure_sta_mode(boot_config);
@@ -503,6 +526,7 @@ BUILD_ASSERT(CONFIG_SIWX91X_NWP_INIT_PRIORITY < CONFIG_KERNEL_INIT_PRIORITY_DEFA
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.enable_xtal_correction = DT_INST_PROP(inst, enable_xtal_correction), \
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.qspi_80mhz_clk = DT_INST_PROP(inst, qspi_80mhz_clk), \
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.antenna_selection = DT_INST_ENUM_IDX(inst, antenna_selection), \
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.clock_frequency = DT_INST_PROP(inst, clock_frequency) \
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}; \
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\
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/* Coprocessor uses value stored in IVT to store its stack. We can't use Z_ISR_DECLARE() */\

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