|
39 | 39 | #size-cells = <1>;
|
40 | 40 | compatible = "intel,pcie";
|
41 | 41 | ranges;
|
| 42 | + |
| 43 | + i2c0: i2c0 { |
| 44 | + compatible = "snps,designware-i2c"; |
| 45 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 46 | + #address-cells = <1>; |
| 47 | + #size-cells = <0>; |
| 48 | + vendor-id = <0x8086>; |
| 49 | + device-id = <0x7acc>; |
| 50 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 51 | + interrupt-parent = <&intc>; |
| 52 | + |
| 53 | + status = "okay"; |
| 54 | + }; |
| 55 | + |
| 56 | + i2c1: i2c1 { |
| 57 | + compatible = "snps,designware-i2c"; |
| 58 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 59 | + #address-cells = <1>; |
| 60 | + #size-cells = <0>; |
| 61 | + vendor-id = <0x8086>; |
| 62 | + device-id = <0x7acd>; |
| 63 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 64 | + interrupt-parent = <&intc>; |
| 65 | + |
| 66 | + status = "okay"; |
| 67 | + }; |
| 68 | + |
| 69 | + i2c2: i2c2 { |
| 70 | + compatible = "snps,designware-i2c"; |
| 71 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 72 | + #address-cells = <1>; |
| 73 | + #size-cells = <0>; |
| 74 | + vendor-id = <0x8086>; |
| 75 | + device-id = <0x7ace>; |
| 76 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 77 | + interrupt-parent = <&intc>; |
| 78 | + |
| 79 | + status = "okay"; |
| 80 | + }; |
| 81 | + |
| 82 | + i2c3: i2c3 { |
| 83 | + compatible = "snps,designware-i2c"; |
| 84 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 85 | + #address-cells = <1>; |
| 86 | + #size-cells = <0>; |
| 87 | + vendor-id = <0x8086>; |
| 88 | + device-id = <0x7acf>; |
| 89 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 90 | + interrupt-parent = <&intc>; |
| 91 | + |
| 92 | + status = "disabled"; |
| 93 | + }; |
| 94 | + |
| 95 | + i2c4: i2c4 { |
| 96 | + compatible = "snps,designware-i2c"; |
| 97 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 98 | + #address-cells = <1>; |
| 99 | + #size-cells = <0>; |
| 100 | + vendor-id = <0x8086>; |
| 101 | + device-id = <0x7afc>; |
| 102 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 103 | + interrupt-parent = <&intc>; |
| 104 | + |
| 105 | + status = "disabled"; |
| 106 | + }; |
| 107 | + |
| 108 | + i2c5: i2c5 { |
| 109 | + compatible = "snps,designware-i2c"; |
| 110 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 111 | + #address-cells = <1>; |
| 112 | + #size-cells = <0>; |
| 113 | + vendor-id = <0x8086>; |
| 114 | + device-id = <0x7afd>; |
| 115 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 116 | + interrupt-parent = <&intc>; |
| 117 | + |
| 118 | + status = "disabled"; |
| 119 | + }; |
| 120 | + |
| 121 | + i2c6: i2c6 { |
| 122 | + compatible = "snps,designware-i2c"; |
| 123 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 124 | + #address-cells = <1>; |
| 125 | + #size-cells = <0>; |
| 126 | + vendor-id = <0x8086>; |
| 127 | + device-id = <0x7ada>; |
| 128 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 129 | + interrupt-parent = <&intc>; |
| 130 | + |
| 131 | + status = "disabled"; |
| 132 | + }; |
| 133 | + |
| 134 | + i2c7: i2c7 { |
| 135 | + compatible = "snps,designware-i2c"; |
| 136 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 137 | + #address-cells = <1>; |
| 138 | + #size-cells = <0>; |
| 139 | + vendor-id = <0x8086>; |
| 140 | + device-id = <0x7adb>; |
| 141 | + interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| 142 | + interrupt-parent = <&intc>; |
| 143 | + |
| 144 | + status = "disabled"; |
| 145 | + }; |
42 | 146 | };
|
43 | 147 |
|
44 | 148 | soc {
|
|
0 commit comments