soc: stm32: add initial soc support for stm32mp1 family

Add the initial SoC support for the STM32MP1 family. The code was
tested on STM32MP157c, but should work on any STM32MP1XX currently
available.

Signed-off-by: Arnaud Pouliquen <[email protected]>

Author: arnopo

soc/arm/st_stm32/stm32mp1/CMakeLists.txt

@@ -0,0 +1,9 @@
+# Copyright (c) 2019 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+zephyr_sources_ifdef(CONFIG_RPROC_RSC_TABLE resource_table.c)

soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series

@@ -0,0 +1,19 @@
+# Kconfig - ST Microelectronics STM32MP1 MCU/MPU line
+#
+# Copyright (c) 2019 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32MP1X
+
+source "soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4"
+
+config SOC_SERIES
+	default "stm32mp1"
+
+config STM32_CORE_CM4
+	bool "define stm32 core"
+	default y
+
+endif # SOC_SERIES_STM32MP1X

soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4

@@ -0,0 +1,17 @@
+# Kconfig - ST Microelectronics STM32MP157C_M4 MCU
+#
+# Copyright (c) 2019 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32MP15_M4
+
+config SOC
+	string
+	default "stm32mp157cxx"
+
+config NUM_IRQS
+	int
+	default 150
+endif # SOC_STM32MP15_M4

soc/arm/st_stm32/stm32mp1/Kconfig.series

@@ -0,0 +1,16 @@
+# Kconfig - ST Microelectronics STM32MP1 MPU series
+#
+# Copyright (c) 2019 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32MP1X
+	bool "STM32MP15 Series MPU"
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_STM32
+	select HAS_STM32CUBE
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_SYSTICK
+	help
+		Enable support for STM32MP1 MPU series

soc/arm/st_stm32/stm32mp1/Kconfig.soc

@@ -0,0 +1,23 @@
+# Kconfig - ST Microelectronics STM32MP1 MPU line
+#
+# Copyright (c) 2019 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32MP1 MPU Selection"
+depends on SOC_SERIES_STM32MP1X
+
+config SOC_STM32MP15_M4
+	bool "STM32MP15_M4"
+
+endchoice
+
+config RPROC_RSC_TABLE
+	bool "coprocessor resource table"
+	default y if RAM_CONSOLE || OPENAMP
+	help
+	  add the resource table in the generated binary. This table is
+	  compatible with linux remote proc framework and OpenAMP library.
+

soc/arm/st_stm32/stm32mp1/dts_fixup.h

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define DT_NUM_IRQ_PRIO_BITS  DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32mp1/linker.ld

@@ -0,0 +1,23 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <arch/arm/cortex_m/scripts/linker.ld>
+
+SECTIONS
+    {
+
+#include <linker/rel-sections.ld>
+#ifdef CONFIG_RPROC_RSC_TABLE
+
+	SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
+	{
+		KEEP(*(.resource_table*))
+    	} GROUP_LINK_IN(ROMABLE_REGION)
+#endif
+}

soc/arm/st_stm32/stm32mp1/resource_table.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+#include "resource_table.h"
+
+extern char ram_console[];
+
+#define __section_t(S)          __attribute__((__section__(#S)))
+#define __resource              __section_t(.resource_table)
+
+#ifdef CONFIG_RAM_CONSOLE
+static volatile struct stm32_resource_table __resource resource_table = {
+	.ver = 1,
+	.num = 1,
+	.offset = {
+		offsetof(struct stm32_resource_table, cm_trace),
+	},
+	.cm_trace = {
+		RSC_TRACE,
+		(uint32_t)ram_console, CONFIG_RAM_CONSOLE_BUFFER_SIZE + 1, 0,
+		"cm4_log",
+	},
+};
+#endif
+
+void resource_table_init(volatile void **table_ptr, int *length)
+{
+	*table_ptr = &resource_table;
+	*length = sizeof(resource_table);
+}
+

soc/arm/st_stm32/stm32mp1/resource_table.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RESOURCE_TABLE_H__
+#define RESOURCE_TABLE_H__
+
+#ifndef OPENAMP_PACKED_BEGIN
+#define OPENAMP_PACKED_BEGIN
+#endif
+
+#ifndef OPENAMP_PACKED_END
+#define OPENAMP_PACKED_END __attribute__((__packed__))
+#endif
+
+/* beginning of section: copied from OpenAMP */
+/**
+ * struct fw_rsc_trace - trace buffer declaration
+ * @da: device address
+ * @len: length (in bytes)
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the trace buffer
+ *
+ * This resource entry provides the host information about a trace buffer
+ * into which the remote remote_proc will write log messages.
+ *
+ * @da specifies the device address of the buffer, @len specifies
+ * its size, and @name may contain a human readable name of the trace buffer.
+ *
+ * After booting the remote remote_proc, the trace buffers are exposed to the
+ * user via debugfs entries (called trace0, trace1, etc..).
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_trace {
+	u32_t type;
+	u32_t da;
+	u32_t len;
+	u32_t reserved;
+	u8_t name[32];
+} OPENAMP_PACKED_END;
+
+OPENAMP_PACKED_BEGIN
+
+enum fw_resource_type {
+	RSC_CARVEOUT = 0,
+	RSC_DEVMEM = 1,
+	RSC_TRACE = 2,
+	RSC_VDEV = 3,
+	RSC_RPROC_MEM = 4,
+	RSC_FW_CHKSUM = 5,
+	RSC_LAST = 6,
+	RSC_VENDOR_START = 128,
+	RSC_VENDOR_END = 512,
+};
+
+/* end of section: copied from OpenAMP */
+
+struct stm32_resource_table {
+	unsigned int ver;
+	unsigned int num;
+	unsigned int reserved[2];
+	unsigned int offset[1];
+
+	/* rpmsg trace entry */
+	struct fw_rsc_trace cm_trace;
+} OPENAMP_PACKED_END;
+
+void resource_table_init(volatile void **table_ptr, int *length);
+
+#endif
+

soc/arm/st_stm32/stm32mp1/soc.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32L4 processor
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32m4_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	z_clearfaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	SystemCoreClock = 209000000;
+
+	return 0;
+}
+
+SYS_INIT(stm32m4_init, PRE_KERNEL_1, 0);