dts: arm: st: stm32h5: set default alt clock for fdcan

Explicitly set the default alt clock for canfd. Without
explicitly setting it the clock subsystem will return
the frequency of the gating clock(APB1).

Signed-off-by: Thomas Stranger <[email protected]>

Author: str4t0m

dts/arm/st/h5/stm32h5.dtsi

@@ -529,7 +529,8 @@
 			reg-names = "m_can", "message_ram";
 			interrupts = <39 0>, <40 0>;
 			interrupt-names = "int0", "int1";
-			clocks = <&rcc STM32_CLOCK(APB1_2, 9)>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 9)>,
+				 <&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
 			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};

dts/arm/st/h5/stm32h523.dtsi

@@ -32,7 +32,8 @@
 			interrupts = <109 0>, <110 0>;
 			interrupt-names = "int0", "int1";
 			/* common clock FDCAN 1 & 2 */
-			clocks = <&rcc STM32_CLOCK(APB1_2, 9)>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 9)>,
+				 <&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
 			bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};

dts/arm/st/h5/stm32h563.dtsi

@@ -50,7 +50,8 @@
 			interrupts = <109 0>, <110 0>;
 			interrupt-names = "int0", "int1";
 			/* common clock FDCAN 1 & 2 */
-			clocks = <&rcc STM32_CLOCK(APB1_2, 9)>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 9)>,
+				 <&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
 			bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};