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| 1 | +# Copyright (c) 2025 Silicon Laboratories Inc. |
| 2 | +# SPDX-License-Identifier: Apache-2.0 |
| 3 | +title: | |
| 4 | + Silicon Labs Series 2 VDAC (Voltage Digital-to-Analog Converter) |
| 5 | +
|
| 6 | +description: | |
| 7 | + The VDAC has two channels, a resolution of 12-bit and a configurable output |
| 8 | + range from 0V to 2.5V. |
| 9 | +
|
| 10 | + The minimal default configuration for the Silabs VDAC node is as follows: |
| 11 | +
|
| 12 | + #include <zephyr/dt-bindings/dac/silabs-vdac.h> |
| 13 | +
|
| 14 | + &vdac0 { |
| 15 | + status = "okay"; |
| 16 | + voltage-reference = "2.5V"; |
| 17 | + channel@0 { |
| 18 | + reg = <0>; |
| 19 | + main-output; |
| 20 | + }; |
| 21 | + }; |
| 22 | +
|
| 23 | + Using the main output is the preferred way for any DAC output. Defines like |
| 24 | + `VDAC0_CH0_MAIN_OUT_PIN` exists in em_device.h to get the dedicated pin for |
| 25 | + your device. |
| 26 | +
|
| 27 | + It is also possible to use the auxiliary output to route the output to other |
| 28 | + peripherals like the IADC or the ACMP, or to the analog bus to output on any GPIO. |
| 29 | + Note that the analog bus multiplexer adds significant impedance, and this option |
| 30 | + may not be suitable for certain loads or dynamic conditions. |
| 31 | +
|
| 32 | + To connect the analog bus to a GPIO, the `pinctrl` driver must be configured to |
| 33 | + allocate an analog bus corresponding to the port and pin of each GPIO input selected. |
| 34 | + The following is an example of how that can be configured: |
| 35 | +
|
| 36 | + #include <zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h> |
| 37 | + #include <zephyr/dt-bindings/dac/silabs-vdac.h> |
| 38 | +
|
| 39 | + &pinctrl { |
| 40 | + vdac0_default: vdac0_default { |
| 41 | + group0 { |
| 42 | + silabs,analog-bus = <ABUS_CDODD0_VDAC0CH0>; |
| 43 | + }; |
| 44 | + group1 { |
| 45 | + silabs,analog-bus = <ABUS_CDEVEN1_VDAC0CH1>; |
| 46 | + }; |
| 47 | + }; |
| 48 | +
|
| 49 | + &vdac0 { |
| 50 | + pinctrl-0 = <&vdac0_default>; |
| 51 | + pinctrl-names = "default"; |
| 52 | + status = "okay"; |
| 53 | + voltage-reference = "1.25V"; |
| 54 | + channel@0 { |
| 55 | + reg = <0>; |
| 56 | + aux-output = <VDAC_OUTPUT_PC1>; |
| 57 | + }; |
| 58 | + channel@1 { |
| 59 | + reg = <1>; |
| 60 | + aux-output = <VDAC_OUTPUT_PC2>; |
| 61 | + }; |
| 62 | + }; |
| 63 | +
|
| 64 | + In the above example, note that the device specific bindings for pinctrl |
| 65 | + were included. This header defines the set of analog bus allocations possible |
| 66 | + for xg24 parts, and similar headers exist for other parts. |
| 67 | +
|
| 68 | +compatible: "silabs,vdac" |
| 69 | + |
| 70 | +include: |
| 71 | + - dac-controller.yaml |
| 72 | + - pinctrl-device.yaml |
| 73 | + |
| 74 | +properties: |
| 75 | + voltage-reference: |
| 76 | + description: | |
| 77 | + Reference voltage to use. |
| 78 | + The default corresponds to the reset value of the register field. |
| 79 | + type: string |
| 80 | + enum: |
| 81 | + - "1.25V" |
| 82 | + - "2.5V" |
| 83 | + - "AVDD" |
| 84 | + - "VREFP" |
| 85 | + default: "1.25V" |
| 86 | + |
| 87 | + warmup-cycles: |
| 88 | + description: | |
| 89 | + Number of prescaled CLK_VDAC + 1 for the DAC to warmup. |
| 90 | + This determines how many clock cycles are needed for the DAC to stabilize |
| 91 | + before it can be used for conversions. |
| 92 | + The default corresponds to the reset value of the register field. |
| 93 | + type: int |
| 94 | + default: 0 |
| 95 | + |
| 96 | + refresh-period-cycles: |
| 97 | + description: | |
| 98 | + Channel refresh period configuration. |
| 99 | + Determines how often the DAC channels are refreshed to maintain accuracy. |
| 100 | + The default corresponds to the reset value of the register field. |
| 101 | + type: int |
| 102 | + enum: [2, 4, 8, 16, 32, 64, 128, 256] |
| 103 | + default: 2 |
| 104 | + |
| 105 | + "#address-cells": |
| 106 | + const: 1 |
| 107 | + |
| 108 | + "#size-cells": |
| 109 | + const: 0 |
| 110 | + |
| 111 | + "#io-channel-cells": |
| 112 | + const: 1 |
| 113 | + |
| 114 | +io-channel-cells: |
| 115 | + - output |
| 116 | + |
| 117 | +child-binding: |
| 118 | + description: | |
| 119 | + Channel configuration. |
| 120 | +
|
| 121 | + properties: |
| 122 | + reg: |
| 123 | + description: | |
| 124 | + Channel identifier. |
| 125 | + type: int |
| 126 | + enum: [0, 1] |
| 127 | + required: true |
| 128 | + |
| 129 | + main-output: |
| 130 | + description: | |
| 131 | + Connects the channel to the dedicated output pin. |
| 132 | + type: boolean |
| 133 | + |
| 134 | + aux-output: |
| 135 | + description: | |
| 136 | + Connects the low-power channel to the auxiliary outputs. |
| 137 | + Connects the channel to the specified output pin on the analog bus. |
| 138 | + type: int |
| 139 | + |
| 140 | + short-output: |
| 141 | + description: | |
| 142 | + Short-circuits the main and auxiliary outputs. |
| 143 | + Set to use high-power mode with auxiliary outputs. |
| 144 | + type: boolean |
| 145 | + |
| 146 | + low-power-mode: |
| 147 | + description: | |
| 148 | + Sets the power mode of the main output to low instead of high. |
| 149 | + type: boolean |
| 150 | + |
| 151 | + high-capacitance-load: |
| 152 | + description: | |
| 153 | + Enables high-capacitance load mode for the DAC channel. |
| 154 | + Only usable without low-power-mode. |
| 155 | + type: boolean |
| 156 | + |
| 157 | + sample-off-mode: |
| 158 | + description: | |
| 159 | + Enables sample-off mode for the DAC channel. |
| 160 | + If enabled, the output is only driven for a limited time per conversion. |
| 161 | + type: boolean |
| 162 | + |
| 163 | + output-hold-cycles: |
| 164 | + description: | |
| 165 | + Time in DAC clock cycles that the output is held for the DAC channel. |
| 166 | + Only usable with sample-off-mode. |
| 167 | + The default corresponds to the reset value of the register field. |
| 168 | + type: int |
| 169 | + default: 0 |
| 170 | + |
| 171 | + refresh-timer: |
| 172 | + description: | |
| 173 | + Enables the refresh timer. |
| 174 | + type: boolean |
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