dts: add support MSPM0Gx51x SOC family

Includes device tree files for SOCs and updates
to common MSPM0 device tree

Signed-off-by: Dylan Philpot <[email protected]>

Author: d-philpot

dts/arm/ti/mspm0/g/mspm0g1518.dtsi

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <mem.h>
+#include <ti/mspm0/g/mspm0gx51x.dtsi>
+
+/ {
+	soc {
+		/*
+		 * Sram Bank 0 (sram0) has ECC checking
+		 * Sram Bank 1 (sram1) is unchecked
+		 */
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
+		};
+
+		sram1: memory@20210000 {
+			reg = <0x20210000 DT_SIZE_K(64)>;
+		};
+
+		flash0: serial-flash@0 {
+			reg = <0x0 DT_SIZE_K(128)>;
+		};
+
+		flash1: serial-flash@40000 {
+			reg = <0x40000 DT_SIZE_K(128)>;
+		};
+
+		flash2: serial-flash@41e00000 {
+			reg = <0x41E00000 DT_SIZE_K(16)>;
+		};
+	};
+};

dts/arm/ti/mspm0/g/mspm0g1519.dtsi

@@ -5,12 +5,28 @@
 
 / {
 	soc {
+		/*
+		 * Sram Bank 0 (sram0) has ECC checking
+		 * Sram Bank 1 (sram1) is unchecked
+		 */
 		sram0: memory@20000000 {
-			reg = <0x20000000 DT_SIZE_K(128)>;
+			reg = <0x20000000 DT_SIZE_K(64)>;
+		};
+
+		sram1: memory@20210000 {
+			reg = <0x20210000 DT_SIZE_K(64)>;
 		};
 
 		flash0: serial-flash@0 {
-			reg = <0x0 DT_SIZE_K(512)>;
+			reg = <0x0 DT_SIZE_K(256)>;
+		};
+
+		flash1: serial-flash@40000 {
+			reg = <0x40000 DT_SIZE_K(256)>;
+		};
+
+		flash2: serial-flash@41e00000 {
+			reg = <0x41E00000 DT_SIZE_K(16)>;
 		};
 	};
 };

dts/arm/ti/mspm0/g/mspm0g3518.dtsi

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <mem.h>
+#include <ti/mspm0/g/mspm0gx51x.dtsi>
+
+/ {
+	soc {
+		/*
+		 * Sram Bank 0 (sram0) has ECC checking
+		 * Sram Bank 1 (sram1) is unchecked
+		 */
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
+		};
+
+		sram1: memory@20210000 {
+			reg = <0x20210000 DT_SIZE_K(64)>;
+		};
+
+		flash0: serial-flash@0 {
+			reg = <0x0 DT_SIZE_K(128)>;
+		};
+
+		flash1: serial-flash@40000 {
+			reg = <0x40000 DT_SIZE_K(128)>;
+		};
+
+		flash2: serial-flash@41e00000 {
+			reg = <0x41E00000 DT_SIZE_K(16)>;
+		};
+	};
+};

dts/arm/ti/mspm0/g/mspm0g3519.dtsi

@@ -5,12 +5,28 @@
 
 / {
 	soc {
+		/*
+		 * Sram Bank 0 (sram0) has ECC checking
+		 * Sram Bank 1 (sram1) is unchecked
+		 */
 		sram0: memory@20000000 {
-			reg = <0x20000000 DT_SIZE_K(128)>;
+			reg = <0x20000000 DT_SIZE_K(64)>;
+		};
+
+		sram1: memory@20210000 {
+			reg = <0x20210000 DT_SIZE_K(64)>;
 		};
 
 		flash0: serial-flash@0 {
-			reg = <0x0 DT_SIZE_K(512)>;
+			reg = <0x0 DT_SIZE_K(256)>;
+		};
+
+		flash1: serial-flash@40000 {
+			reg = <0x40000 DT_SIZE_K(256)>;
+		};
+
+		flash2: serial-flash@41e00000 {
+			reg = <0x41E00000 DT_SIZE_K(16)>;
 		};
 	};
 };

dts/arm/ti/mspm0/g/mspm0gx51x.dtsi

@@ -1,3 +1,16 @@
 /* SPDX-License-Identifier: Apache-2.0 */
 
 #include <ti/mspm0/g/mspm0g.dtsi>
+
+/{
+	soc {
+		gpioc: gpio@400a4000 {
+			compatible = "ti,mspm0-gpio";
+			reg = <0x400a4000 0x2000>;
+			interrupts = <1 0>;
+			status = "disabled";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};